NAME
vbs - simulate Verilog behavioral descriptions
SYNOPSYS
vbs [OPTION]... SOURCE...
DESCRIPTION
Simulate SOURCE files.
-a, --ascii_dump
-
Dump using ascii format.
-c, --compile-only
-
Stop after compilation, do not simulate. Currently, the compiled object file cannot be used for anything useful.
-d, --debug-enable=TYPE
-
Enables the specified TYPE of debug output, where TYPE is one of the following: sim_state, parser, symbol_table, time_wheel, event, user[1-4], userx. This option may be used multiple times, but is only available if debug is enabled.
-D, --define
-
Define macro for preprocessing (only for vpp).
-E, --preprocess-only
-
Stop after preprocessing, do not compile.
-I, --incdir
-
Search directory for include files (only for vpp).
-l, --debug-outfile=FILE
-
Specifies the file to write debug output. If not specified and debug is enabled, output will go to stdout. Available only if debug is enabled.
-q, --quiet
-
Do not output statistics. This option may be used multiple times.
-v, --vcd_dump
-
Dump using VCD format.
-x, --delays={min,typ,max}
-z #
-
Compress dumpfile with zlib at the specified compression level, # (from 1 to 9).
-h, --help
-
Display this message.
AUTHOR
Written by Lay Hoon Tho and Jimen Ching.
This manual page was written by Shaun Jackman <[email protected]> for the Debian system.
REPORTING BUGS
Report bugs to Jimen Ching <[email protected]>.
COPYRIGHT
Copyright 1995, 1996, 1997, 2001 Lay Hoon Tho, Jimen Ching
This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
SEE ALSO
http://www.flex.com/~jching/