---
name: "struct_nand_sdr_timings"
section: "9"
platform: "linux"
package: "linux-manual-4.9"
version: "4.9.228-1"
release: "Debian 9 (Stretch)"
platforms: ["linux"]
url: "https://new.carta.tech/struct_nand_sdr_timings"
---

# struct\_nand\_sdr\_timings(9)

SDR NAND chip timings

## NAME

struct\_nand\_sdr\_timings - SDR NAND chip timings

## SYNOPSIS

```
struct nand_sdr_timings {
  u32 tALH_min;
  u32 tADL_min;
  u32 tALS_min;
  u32 tAR_min;
  u32 tCEA_max;
  u32 tCH_min;
  u32 tCHZ_max;
  u32 tCLH_min;
  u32 tCLR_min;
  u32 tCLS_min;
  u32 tCOH_min;
  u32 tCS_min;
  u32 tDH_min;
  u32 tDS_min;
  u32 tFEAT_max;
  u32 tIR_min;
  u32 tITC_max;
  u32 tRC_min;
  u32 tREA_max;
  u32 tREH_min;
  u32 tRHOH_min;
  u32 tRHW_min;
  u32 tRHZ_max;
  u32 tRLOH_min;
  u32 tRP_min;
  u32 tRR_min;
  u64 tRST_max;
  u32 tWB_max;
  u32 tWC_min;
  u32 tWH_min;
  u32 tWHR_min;
  u32 tWP_min;
  u32 tWW_min;
};
```

## MEMBERS

tALH\_min

ALE hold time

tADL\_min

ALE to data loading time

tALS\_min

ALE setup time

tAR\_min

ALE to RE# delay

tCEA\_max

CE# access time

tCH\_min

CE# hold time

tCHZ\_max

CE# high to output hi-Z

tCLH\_min

CLE hold time

tCLR\_min

CLE to RE# delay

tCLS\_min

CLE setup time

tCOH\_min

CE# high to output hold

tCS\_min

CE# setup time

tDH\_min

Data hold time

tDS\_min

Data setup time

tFEAT\_max

Busy time for Set Features and Get Features

tIR\_min

Output hi-Z to RE# low

tITC\_max

Interface and Timing Mode Change time

tRC\_min

RE# cycle time

tREA\_max

RE# access time

tREH\_min

RE# high hold time

tRHOH\_min

RE# high to output hold

tRHW\_min

RE# high to WE# low

tRHZ\_max

RE# high to output hi-Z

tRLOH\_min

RE# low to output hold

tRP\_min

RE# pulse width

tRR\_min

Ready to RE# low (data only)

tRST\_max

Device reset time, measured from the falling edge of R/B# to the rising edge of R/B#.

tWB\_max

WE# high to SR\[6\] low

tWC\_min

WE# cycle time

tWH\_min

WE# high hold time

tWHR\_min

WE# high to RE# low

tWP\_min

WE# pulse width

tWW\_min

WP# transition to WE# low

## DESCRIPTION

This struct defines the timing requirements of a SDR NAND chip. These information can be found in every NAND datasheets and the timings meaning are described in the ONFI specifications: www.onfi.org/~/media/ONFI/specs/onfi\_3\_1\_spec.pdf (chapter 4.15 Timing Parameters)

All these timings are expressed in picoseconds.

## AUTHOR

**Thomas Gleixner** \<tglx@linutronix.de\>

Author.

## COPYRIGHT