---
name: "qtrvsim_cli"
section: "1"
platform: "linux"
package: "qtrvsim"
version: "0.9.8-1"
release: "Debian 13 (Trixie)"
platforms: ["linux"]
url: "https://new.carta.tech/qtrvsim_cli"
---

# qtrvsim\_cli(1)

RISC-V CPU simulator for education

## NAME

qtrvsim\_cli - RISC-V CPU simulator for education

## SYNOPSIS

**qtrvsim\_cli** \[*options*\] *FILE*

## DESCRIPTION

QtRvSim CLI machine simulator

## OPTIONS

- **-h**, **--help**

  Displays help on commandline options.

- **--help-all**

  Displays help including Qt specific options.

- **-v**, **--version**

  Displays version information.

- **--asm**

  Treat provided file argument as assembler source.

- **--pipelined**

  Configure CPU to use five stage pipeline.

- **--no-delay-slot**

  Disable jump delay slot.

- **--hazard-unit** \<HUKIND\>

  Specify hazard unit implementation \[none\|stall\|forward\].

- **--trace-fetch**, **--tr-fetch**

  Trace fetched instruction (for both pipelined and not core).

- **--trace-decode**, **--tr-decode**

  Trace instruction in decode stage. (only for pipelined core)

- **--trace-execute**, **--tr-execute**

  Trace instruction in execute stage. (only for pipelined core)

- **--trace-memory**, **--tr-memory**

  Trace instruction in memory stage. (only for pipelined core)

- **--trace-writeback**, **--tr-writeback**

  Trace instruction in write back stage. (only for pipelined core)

- **--trace-pc**, **--tr-pc**

  Print program counter register changes.

- **--trace-wrmem**, **--tr-wr**

  Trace writes into memory.

- **--trace-rdmem**, **--tr-rd**

  Trace reads from memory.

- **--trace-gp**, **--tr-gp** \<REG\>

  Print general purpose register changes. You can use \* for all registers.

- **--dump-to-json** \<FNAME\>

  Configure reportor dump to json file.

- **--dump-registers**, **--d-regs**

  Dump registers state at program exit.

- **--dump-cache-stats**

  Dump cache statistics at program exit.

- **--dump-cycles**

  Dump number of CPU cycles till program end.

- **--dump-range** \<START,LENGTH,FNAME\>

  Dump memory range.

- **--load-range** \<START,FNAME\>

  Load memory range.

- **--expect-fail**

  Expect that program causes CPU trap and fail if it doesn't.

- **--fail-match** \<TRAP\>

  Program should exit with exactly this CPU TRAP. Possible values are I(unsupported Instruction), A(Unsupported ALU operation), O(Overflow/underflow) and J(Unaligned Jump). You can freely combine them. Using this implies expect-fail option.

- **--d-cache** \<DCACHE\>

  Data cache. Format policy,sets,words\_in\_blocks,associativity where policy is random/lru/lfu

- **--i-cache** \<ICACHE\>

  Instruction cache. Format policy,sets,words\_in\_blocks,associativity where policy is random/lru/lfu

- **--l2-cache** \<L2CACHE\>

  L2 cache. Format policy,sets,words\_in\_blocks,associativity where policy is random/lru/lfu

- **--read-time** \<RTIME\>

  Memory read access time (cycles).

- **--write-time** \<WTIME\>

  Memory read access time (cycles).

- **--burst-time** \<BTIME\>

  Memory read access time (cycles).

- **--serial-in**, **--serin** \<FNAME\>

  File connected to the serial port input.

- **--serial-out**, **--serout** \<FNAME\>

  File connected to the serial port output.

- **--os-emulation**, **--osemu**

  Operating system emulation.

- **--std-out**, **--stdout** \<FNAME\>

  File connected to the syscall standard output.

- **--os-fs-root**, **--osfsroot** \<DIR\>

  Emulated system root/prefix for opened files

- **--isa-variant**, **--isavariant** \<STR\>

  Instruction set to emulate (default RV32IMA)

- **--cycle-limit** \<NUMBER\>

  Limit execution to specified maximum clock cycles

### Arguments:

- FILE

  Input ELF executable file or assembler source

## SEE ALSO

The full documentation for **qtrvsim\_cli** is maintained as a Texinfo manual.  If the **info** and **qtrvsim\_cli** programs are properly installed at your site, the command

-

  **info qtrvsim\_cli**

should give you access to the complete manual.