padlock4
Via and zhaoxin cpu crypto driver
Usage
To compile this driver into the kernel, place the following lines in your kernel configuration file:
device crypto device padlock
Alternatively, to load the driver as a module at boot time, place the following line in loader.conf(5):
padlock_load="YES"
Overview
The C3 and Eden processor series from VIA include hardware acceleration for AES. The C7 series includes hardware acceleration for AES, SHA1, SHA256 and RSA. All of the above processor series include a hardware random number generator.
The padlock driver registers itself to accelerate AES operations and, if available, HMAC/SHA1 and HMAC/SHA256 for crypto(4). It also registers itself to accelerate other HMAC algorithms, although there is no hardware acceleration for those algorithms. This is only needed so padlock can work with ipsec(4).
The hardware random number generator supplies data for the kernel random(4) subsystem.
Hardware
The padlock driver supports the AES, RNG, RSA, SHA-1, and SHA-2 engine found on:
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Via Technologies Nano X2, Nano, C7, C3, and Eden CPUs
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Some Zhaoxin CPUs
Releases
38 releases since FreeBSD 8.1-RELEASE; the text changed 25 times.