--- name: "libpfm_intel_spr" section: "3" platform: "linux" package: "libpfm" version: "4.14.1-1" release: "Arch Linux 2026-11-01" platforms: ["linux"] url: "https://new.carta.tech/libpfm_intel_spr" --- # libpfm\_intel\_spr(3) support for Intel SapphireRapids core PMU ## NAME libpfm\_intel\_spr - support for Intel SapphireRapids core PMU ## SYNOPSIS ``` #include PMU name: spr PMU desc: Intel SapphireRapids ``` ## DESCRIPTION The library supports the Intel SapphireRapids core PMU. It should be noted that this PMU model only covers each core's PMU and not the socket level PMU. On SapphireRapids, the number of generic counters depends on the Hyperthreading (HT) mode. The **pfm\_get\_pmu\_info()** function returns the maximum number of generic counters in **num\_cntrs**. ## MODIFIERS The following modifiers are supported on Intel SapphireRapids processors: - **u** Measure at user level which includes privilege levels 1, 2, 3. This corresponds to **PFM\_PLM3**. This is a boolean modifier. - **k** Measure at kernel level which includes privilege level 0. This corresponds to **PFM\_PLM0**. This is a boolean modifier. - **i** Invert the meaning of the event. The counter will now count cycles in which the event is **not** occurring. This is a boolean modifier - **e** Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. - **c** Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range \[0:255\]. - **ldlat** Pass a latency threshold to the MEM\_TRANS\_RETIRED:LOAD\_LATENCY event. This is an integer attribute that must be in the range \[1:65535\]. It is required for this event. Note that the event must be used with precise sampling (PEBS). - **intx** Monitor the event only when executing inside a transactional memory region (in tx). Event does not count otherwise. This is a boolean modifiers. Default value is 0. - **intxcp** Do not count occurrences of the event when they are inside an aborted transactional memory region. This is a boolean modifier. Default value is 0. - **fe\_thres** This modifier is for the FRONTEND\_RETIRED event only. It defines the period in core cycles after which the IDQ\_\*\_BUBBLES umask counts. It acts as a threshold, i.e., at least a period of N core cycles where the frontend did not deliver X uops. It can only be used with the IDQ\_\*\_BUBBLES umasks. If not specified, the default threshold value is 1 cycle. the valid values are in \[1-4095\]. ## OFFCORE\_RESPONSE events Intel SapphireRapids supports two encodings for offcore\_response events. In the library, these are called OFFCORE\_RESPONSE\_0 and OFFCORE\_RESPONSE\_1. Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. Thus, in case multiple offcore\_response events are monitored simultaneously, the operating system needs to manage the sharing of that extra register. The offcore\_response events are exposed as a normal events by the library. The extra settings are exposed as regular umasks. The library takes care of encoding the events according to the underlying kernel interface. On Intel SapphireRapids unlike older processors, the event is treated as a regular event with a flat set of umasks to choose from. It is not possible to combine the various requests, supplier, snoop bits anymore. Therefore the library offers the list of validated combinations as per Intel's official event list. ## Topdown via PERF\_METRICS Intel SapphireRapids supports the PERF\_METRICS MSR which provides support for Topdown Level 1 and 2 via a single PMU counter. This special counter provides percentages of slots for each metric. This feature must be used in conjunction with fixed counter 3 which counts SLOTS in order to work properly. The Linux kernel exposes PERF\_METRICS metrics as individual pseudo events counting in slots unit however to operate correctly all events must be programmed together. The Linux kernel requires all PERF\_METRICS events to be programmed as a single event group with the first event as SLOTS required. Example: '{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown-fetch-lat,topdown-mem-bound}'. Libpfm4 provides acces to the PERF\_METRICS pseudo events via a dedicated event called **TOPDOWN\_M**. This event uses the pseudo encodings assigned by the Linux kernel to PERF\_METRICS pseudo events. Using these encodings ensures the kernel detects them as targeting the PERF\_METRICS MSR. Note that libpfm4 only provides the encodings and that it is up the user on Linux to group them and order them properly for the perf\_events interface. There exists generic counter encodings for most of the Topdown metrics and libpfm4 provides support for those via the **TOPDOWN** event. Note that all subevents of **TOPDOWN\_M** use fixed counters which have, by definition, no actual event codes. The library uses the Linux pseudo event codes for them, even when compiled on non Linux operating systems.The same holds true for any fixed counters pseudo event exported by libpfm4. ## AUTHORS ``` Stephane Eranian ```