--- name: "libcpuid" section: "3" platform: "linux" package: "libcpuid" version: "0.8.2-1" release: "Arch Linux 2026-11-01" platforms: ["linux"] url: "https://new.carta.tech/libcpuid" --- # libcpuid(3) LibCPUID - LibCPUID provides CPU identification. ## NAME libcpuid - LibCPUID \- LibCPUID provides CPU identification. ## SYNOPSIS ### Data Structures struct **cpu\_raw\_data\_t**\ Contains just the raw CPUID data. struct **cpu\_raw\_data\_array\_t**\ Contains an array of raw CPUID data. struct **cpu\_sgx\_t**\ This contains information about SGX features of the processor Example usage: struct **x86\_id\_t**\ Contains x86 specific info. struct **arm\_id\_t**\ Contains ARM specific info. struct **cpu\_id\_t**\ This contains the recognized CPU features/info. union **cpu\_id\_t::\[union\].\_\_unnamed0\_\_**\ struct **cpu\_list\_t**\ a structure that holds a list of processor names struct **cpu\_epc\_t**\ The return value of **cpuid\_get\_epc()**. struct **cpu\_mark\_t**\ Internal structure, used in cpu\_tsc\_mark, cpu\_tsc\_unmark and cpu\_clock\_by\_mark. struct **system\_id\_t**\ This contains the recognized features/info for all CPUs on the system. ### Macros \#define **LIBCPUID\_DEPRECATED**(message)\ \#define **NUM\_CPU\_VENDORS** NUM\_CPU\_VENDORS\ \#define **NUM\_CPU\_ARCHITECTURES** NUM\_CPU\_ARCHITECTURES\ \#define **NUM\_FEATURE\_LEVELS** NUM\_FEATURE\_LEVELS\ \#define **NUM\_CPU\_PURPOSES** NUM\_CPU\_PURPOSES\ \#define **NUM\_HYPERVISOR\_VENDORS** NUM\_HYPERVISOR\_VENDORS\ \#define **CPU\_INVALID\_VALUE** 0x3fffffff\ ### Typedefs typedef void(\*) **libcpuid\_warn\_fn\_t**(const char \*msg)\ ### Enumerations enum **cpu\_vendor\_t** { **VENDOR\_INTEL** = 0, **VENDOR\_AMD**, **VENDOR\_CYRIX**, **VENDOR\_NEXGEN**, **VENDOR\_TRANSMETA**, **VENDOR\_UMC**, **VENDOR\_CENTAUR**, **VENDOR\_RISE**, **VENDOR\_SIS**, **VENDOR\_NSC**, **VENDOR\_HYGON**, **VENDOR\_ARM**, **VENDOR\_BROADCOM**, **VENDOR\_CAVIUM**, **VENDOR\_DEC**, **VENDOR\_FUJITSU**, **VENDOR\_HISILICON**, **VENDOR\_INFINEON**, **VENDOR\_FREESCALE**, **VENDOR\_NVIDIA**, **VENDOR\_APM**, **VENDOR\_QUALCOMM**, **VENDOR\_SAMSUNG**, **VENDOR\_MARVELL**, **VENDOR\_APPLE**, **VENDOR\_FARADAY**, **VENDOR\_MICROSOFT**, **VENDOR\_PHYTIUM**, **VENDOR\_AMPERE**, **NUM\_CPU\_VENDORS**, **VENDOR\_UNKNOWN** = -1 }\ CPU vendor, as guessed from the Vendor String. enum **cpu\_architecture\_t** { **ARCHITECTURE\_X86** = 0, **ARCHITECTURE\_ARM**, **NUM\_CPU\_ARCHITECTURES**, **ARCHITECTURE\_UNKNOWN** = -1 }\ CPU architecture. enum **cpu\_feature\_level\_t** { **FEATURE\_LEVEL\_I386**, **FEATURE\_LEVEL\_I486**, **FEATURE\_LEVEL\_I586**, **FEATURE\_LEVEL\_I686**, **FEATURE\_LEVEL\_X86\_64\_V1**, **FEATURE\_LEVEL\_X86\_64\_V2**, **FEATURE\_LEVEL\_X86\_64\_V3**, **FEATURE\_LEVEL\_X86\_64\_V4**, **FEATURE\_LEVEL\_ARM\_V1** = 100, **FEATURE\_LEVEL\_ARM\_V2**, **FEATURE\_LEVEL\_ARM\_V3**, **FEATURE\_LEVEL\_ARM\_V4**, **FEATURE\_LEVEL\_ARM\_V4T**, **FEATURE\_LEVEL\_ARM\_V5**, **FEATURE\_LEVEL\_ARM\_V5T**, **FEATURE\_LEVEL\_ARM\_V5TE**, **FEATURE\_LEVEL\_ARM\_V5TEJ**, **FEATURE\_LEVEL\_ARM\_V6**, **FEATURE\_LEVEL\_ARM\_V6\_M**, **FEATURE\_LEVEL\_ARM\_V7\_A**, **FEATURE\_LEVEL\_ARM\_V7\_M**, **FEATURE\_LEVEL\_ARM\_V7\_R**, **FEATURE\_LEVEL\_ARM\_V7E\_M**, **FEATURE\_LEVEL\_ARM\_V8\_0\_A**, **FEATURE\_LEVEL\_ARM\_V8\_0\_M**, **FEATURE\_LEVEL\_ARM\_V8\_0\_R**, **FEATURE\_LEVEL\_ARM\_V8\_1\_A**, **FEATURE\_LEVEL\_ARM\_V8\_1\_M**, **FEATURE\_LEVEL\_ARM\_V8\_2\_A**, **FEATURE\_LEVEL\_ARM\_V8\_3\_A**, **FEATURE\_LEVEL\_ARM\_V8\_4\_A**, **FEATURE\_LEVEL\_ARM\_V8\_5\_A**, **FEATURE\_LEVEL\_ARM\_V8\_6\_A**, **FEATURE\_LEVEL\_ARM\_V8\_7\_A**, **FEATURE\_LEVEL\_ARM\_V8\_8\_A**, **FEATURE\_LEVEL\_ARM\_V8\_9\_A**, **FEATURE\_LEVEL\_ARM\_V9\_0\_A**, **FEATURE\_LEVEL\_ARM\_V9\_1\_A**, **FEATURE\_LEVEL\_ARM\_V9\_2\_A**, **FEATURE\_LEVEL\_ARM\_V9\_3\_A**, **FEATURE\_LEVEL\_ARM\_V9\_4\_A**, **FEATURE\_LEVEL\_ARM\_V9\_5\_A**, **NUM\_FEATURE\_LEVELS**, **FEATURE\_LEVEL\_UNKNOWN** = -1 }\ CPU feature level. enum **cpu\_purpose\_t** { **PURPOSE\_GENERAL** = 0, **PURPOSE\_PERFORMANCE**, **PURPOSE\_EFFICIENCY**, **PURPOSE\_LP\_EFFICIENCY**, **PURPOSE\_U\_PERFORMANCE**, **NUM\_CPU\_PURPOSES** }\ CPU purpose. enum **hypervisor\_vendor\_t** { **HYPERVISOR\_NONE** = 0, **HYPERVISOR\_BHYVE**, **HYPERVISOR\_HYPERV**, **HYPERVISOR\_KVM**, **HYPERVISOR\_PARALLELS**, **HYPERVISOR\_QEMU**, **HYPERVISOR\_VIRTUALBOX**, **HYPERVISOR\_VMWARE**, **HYPERVISOR\_XEN**, **NUM\_HYPERVISOR\_VENDORS**, **HYPERVISOR\_UNKNOWN** = -1 }\ Hypervisor vendor, as guessed from the CPU\_FEATURE\_HYPERVISOR flag. enum **cpu\_feature\_t** { **CPU\_FEATURE\_FPU** = 0, **CPU\_FEATURE\_VME**, **CPU\_FEATURE\_DE**, **CPU\_FEATURE\_PSE**, **CPU\_FEATURE\_TSC**, **CPU\_FEATURE\_MSR**, **CPU\_FEATURE\_PAE**, **CPU\_FEATURE\_MCE**, **CPU\_FEATURE\_CX8**, **CPU\_FEATURE\_APIC**, **CPU\_FEATURE\_MTRR**, **CPU\_FEATURE\_SEP**, **CPU\_FEATURE\_PGE**, **CPU\_FEATURE\_MCA**, **CPU\_FEATURE\_CMOV**, **CPU\_FEATURE\_PAT**, **CPU\_FEATURE\_PSE36**, **CPU\_FEATURE\_PN**, **CPU\_FEATURE\_CLFLUSH**, **CPU\_FEATURE\_DTS**, **CPU\_FEATURE\_ACPI**, **CPU\_FEATURE\_MMX**, **CPU\_FEATURE\_FXSR**, **CPU\_FEATURE\_SSE**, **CPU\_FEATURE\_SSE2**, **CPU\_FEATURE\_SS**, **CPU\_FEATURE\_HT**, **CPU\_FEATURE\_TM**, **CPU\_FEATURE\_IA64**, **CPU\_FEATURE\_PBE**, **CPU\_FEATURE\_PNI**, **CPU\_FEATURE\_PCLMUL**, **CPU\_FEATURE\_DTS64**, **CPU\_FEATURE\_MONITOR**, **CPU\_FEATURE\_DS\_CPL**, **CPU\_FEATURE\_VMX**, **CPU\_FEATURE\_SMX**, **CPU\_FEATURE\_EST**, **CPU\_FEATURE\_TM2**, **CPU\_FEATURE\_SSSE3**, **CPU\_FEATURE\_CID**, **CPU\_FEATURE\_CX16**, **CPU\_FEATURE\_XTPR**, **CPU\_FEATURE\_PDCM**, **CPU\_FEATURE\_DCA**, **CPU\_FEATURE\_SSE4\_1**, **CPU\_FEATURE\_SSE4\_2**, **CPU\_FEATURE\_SYSCALL**, **CPU\_FEATURE\_XD**, **CPU\_FEATURE\_MOVBE**, **CPU\_FEATURE\_POPCNT**, **CPU\_FEATURE\_AES**, **CPU\_FEATURE\_XSAVE**, **CPU\_FEATURE\_OSXSAVE**, **CPU\_FEATURE\_AVX**, **CPU\_FEATURE\_MMXEXT**, **CPU\_FEATURE\_3DNOW**, **CPU\_FEATURE\_3DNOWEXT**, **CPU\_FEATURE\_NX**, **CPU\_FEATURE\_FXSR\_OPT**, **CPU\_FEATURE\_RDTSCP**, **CPU\_FEATURE\_LM**, **CPU\_FEATURE\_LAHF\_LM**, **CPU\_FEATURE\_CMP\_LEGACY**, **CPU\_FEATURE\_SVM**, **CPU\_FEATURE\_ABM**, **CPU\_FEATURE\_MISALIGNSSE**, **CPU\_FEATURE\_SSE4A**, **CPU\_FEATURE\_3DNOWPREFETCH**, **CPU\_FEATURE\_OSVW**, **CPU\_FEATURE\_IBS**, **CPU\_FEATURE\_SSE5**, **CPU\_FEATURE\_SKINIT**, **CPU\_FEATURE\_WDT**, **CPU\_FEATURE\_TS**, **CPU\_FEATURE\_FID**, **CPU\_FEATURE\_VID**, **CPU\_FEATURE\_TTP**, **CPU\_FEATURE\_TM\_AMD**, **CPU\_FEATURE\_STC**, **CPU\_FEATURE\_100MHZSTEPS**, **CPU\_FEATURE\_HWPSTATE**, **CPU\_FEATURE\_CONSTANT\_TSC**, **CPU\_FEATURE\_XOP**, **CPU\_FEATURE\_FMA3**, **CPU\_FEATURE\_FMA4**, **CPU\_FEATURE\_TBM**, **CPU\_FEATURE\_F16C**, **CPU\_FEATURE\_RDRAND**, **CPU\_FEATURE\_X2APIC**, **CPU\_FEATURE\_CPB**, **CPU\_FEATURE\_APERFMPERF**, **CPU\_FEATURE\_PFI**, **CPU\_FEATURE\_PA**, **CPU\_FEATURE\_AVX2**, **CPU\_FEATURE\_BMI1**, **CPU\_FEATURE\_BMI2**, **CPU\_FEATURE\_HLE**, **CPU\_FEATURE\_RTM**, **CPU\_FEATURE\_AVX512F**, **CPU\_FEATURE\_AVX512DQ**, **CPU\_FEATURE\_AVX512PF**, **CPU\_FEATURE\_AVX512ER**, **CPU\_FEATURE\_AVX512CD**, **CPU\_FEATURE\_SHA\_NI**, **CPU\_FEATURE\_AVX512BW**, **CPU\_FEATURE\_AVX512VL**, **CPU\_FEATURE\_SGX**, **CPU\_FEATURE\_RDSEED**, **CPU\_FEATURE\_ADX**, **CPU\_FEATURE\_AVX512VNNI**, **CPU\_FEATURE\_AVX512VBMI**, **CPU\_FEATURE\_AVX512VBMI2**, **CPU\_FEATURE\_HYPERVISOR**, **CPU\_FEATURE\_SWAP**, **CPU\_FEATURE\_THUMB**, **CPU\_FEATURE\_ADVMULTU**, **CPU\_FEATURE\_ADVMULTS**, **CPU\_FEATURE\_JAZELLE**, **CPU\_FEATURE\_DEBUGV6**, **CPU\_FEATURE\_DEBUGV6P1**, **CPU\_FEATURE\_THUMB2**, **CPU\_FEATURE\_DEBUGV7**, **CPU\_FEATURE\_DEBUGV7P1**, **CPU\_FEATURE\_THUMBEE**, **CPU\_FEATURE\_DIVIDE**, **CPU\_FEATURE\_LPAE**, **CPU\_FEATURE\_PMUV1**, **CPU\_FEATURE\_PMUV2**, **CPU\_FEATURE\_ASID16**, **CPU\_FEATURE\_ADVSIMD**, **CPU\_FEATURE\_CRC32**, **CPU\_FEATURE\_CSV2\_1P1**, **CPU\_FEATURE\_CSV2\_1P2**, **CPU\_FEATURE\_CSV2\_2**, **CPU\_FEATURE\_CSV2\_3**, **CPU\_FEATURE\_DOUBLELOCK**, **CPU\_FEATURE\_ETS2**, **CPU\_FEATURE\_FP**, **CPU\_FEATURE\_MIXEDEND**, **CPU\_FEATURE\_MIXEDENDEL0**, **CPU\_FEATURE\_PMULL**, **CPU\_FEATURE\_PMUV3**, **CPU\_FEATURE\_SHA1**, **CPU\_FEATURE\_SHA256**, **CPU\_FEATURE\_NTLBPA**, **CPU\_FEATURE\_HAFDBS**, **CPU\_FEATURE\_HPDS**, **CPU\_FEATURE\_LOR**, **CPU\_FEATURE\_LSE**, **CPU\_FEATURE\_PAN**, **CPU\_FEATURE\_PMUV3P1**, **CPU\_FEATURE\_RDM**, **CPU\_FEATURE\_VHE**, **CPU\_FEATURE\_VMID16**, **CPU\_FEATURE\_AA32HPD**, **CPU\_FEATURE\_AA32I8MM**, **CPU\_FEATURE\_DPB**, **CPU\_FEATURE\_DEBUGV8P2**, **CPU\_FEATURE\_F32MM**, **CPU\_FEATURE\_F64MM**, **CPU\_FEATURE\_FP16**, **CPU\_FEATURE\_HPDS2**, **CPU\_FEATURE\_I8MM**, **CPU\_FEATURE\_IESB**, **CPU\_FEATURE\_LPA**, **CPU\_FEATURE\_LSMAOC**, **CPU\_FEATURE\_LVA**, **CPU\_FEATURE\_PAN2**, **CPU\_FEATURE\_RAS**, **CPU\_FEATURE\_SHA3**, **CPU\_FEATURE\_SHA512**, **CPU\_FEATURE\_SM3**, **CPU\_FEATURE\_SM4**, **CPU\_FEATURE\_SPE**, **CPU\_FEATURE\_SVE**, **CPU\_FEATURE\_TTCNP**, **CPU\_FEATURE\_UAO**, **CPU\_FEATURE\_XNX**, **CPU\_FEATURE\_CCIDX**, **CPU\_FEATURE\_CONSTPACFIELD**, **CPU\_FEATURE\_EPAC**, **CPU\_FEATURE\_FCMA**, **CPU\_FEATURE\_FPAC**, **CPU\_FEATURE\_FPACCOMBINE**, **CPU\_FEATURE\_JSCVT**, **CPU\_FEATURE\_LRCPC**, **CPU\_FEATURE\_PACIMP**, **CPU\_FEATURE\_PACQARMA3**, **CPU\_FEATURE\_PACQARMA5**, **CPU\_FEATURE\_PAUTH**, **CPU\_FEATURE\_SPEV1P1**, **CPU\_FEATURE\_AMUV1**, **CPU\_FEATURE\_BBM**, **CPU\_FEATURE\_DIT**, **CPU\_FEATURE\_DEBUGV8P4**, **CPU\_FEATURE\_DOTPROD**, **CPU\_FEATURE\_DOUBLEFAULT**, **CPU\_FEATURE\_FHM**, **CPU\_FEATURE\_FLAGM**, **CPU\_FEATURE\_IDST**, **CPU\_FEATURE\_LRCPC2**, **CPU\_FEATURE\_LSE2**, **CPU\_FEATURE\_MPAM**, **CPU\_FEATURE\_PMUV3P4**, **CPU\_FEATURE\_RASV1P1**, **CPU\_FEATURE\_S2FWB**, **CPU\_FEATURE\_SEL2**, **CPU\_FEATURE\_TLBIOS**, **CPU\_FEATURE\_TLBIRANGE**, **CPU\_FEATURE\_TRF**, **CPU\_FEATURE\_TTL**, **CPU\_FEATURE\_TTST**, **CPU\_FEATURE\_BTI**, **CPU\_FEATURE\_CSV2**, **CPU\_FEATURE\_CSV3**, **CPU\_FEATURE\_DPB2**, **CPU\_FEATURE\_E0PD**, **CPU\_FEATURE\_EVT**, **CPU\_FEATURE\_EXS**, **CPU\_FEATURE\_FRINTTS**, **CPU\_FEATURE\_FLAGM2**, **CPU\_FEATURE\_MTE**, **CPU\_FEATURE\_MTE2**, **CPU\_FEATURE\_PMUV3P5**, **CPU\_FEATURE\_RNG**, **CPU\_FEATURE\_RNG\_TRAP**, **CPU\_FEATURE\_SB**, **CPU\_FEATURE\_SPECRES**, **CPU\_FEATURE\_SSBS**, **CPU\_FEATURE\_SSBS2**, **CPU\_FEATURE\_AA32BF16**, **CPU\_FEATURE\_AMUV1P1**, **CPU\_FEATURE\_BF16**, **CPU\_FEATURE\_DGH**, **CPU\_FEATURE\_ECV**, **CPU\_FEATURE\_FGT**, **CPU\_FEATURE\_HPMN0**, **CPU\_FEATURE\_MPAMV0P1**, **CPU\_FEATURE\_MPAMV1P1**, **CPU\_FEATURE\_MTPMU**, **CPU\_FEATURE\_PAUTH2**, **CPU\_FEATURE\_TWED**, **CPU\_FEATURE\_AFP**, **CPU\_FEATURE\_EBF16**, **CPU\_FEATURE\_HCX**, **CPU\_FEATURE\_LPA2**, **CPU\_FEATURE\_LS64**, **CPU\_FEATURE\_LS64\_ACCDATA**, **CPU\_FEATURE\_LS64\_V**, **CPU\_FEATURE\_MTE3**, **CPU\_FEATURE\_MTE\_ASYM\_FAULT**, **CPU\_FEATURE\_PAN3**, **CPU\_FEATURE\_PMUV3P7**, **CPU\_FEATURE\_RPRES**, **CPU\_FEATURE\_SPEV1P2**, **CPU\_FEATURE\_WFXT**, **CPU\_FEATURE\_XS**, **CPU\_FEATURE\_CMOW**, **CPU\_FEATURE\_DEBUGV8P8**, **CPU\_FEATURE\_HBC**, **CPU\_FEATURE\_MOPS**, **CPU\_FEATURE\_NMI**, **CPU\_FEATURE\_PMUV3P8**, **CPU\_FEATURE\_SCTLR2**, **CPU\_FEATURE\_SPEV1P3**, **CPU\_FEATURE\_TCR2**, **CPU\_FEATURE\_TIDCP1**, **CPU\_FEATURE\_ADERR**, **CPU\_FEATURE\_AIE**, **CPU\_FEATURE\_ANERR**, **CPU\_FEATURE\_ATS1A**, **CPU\_FEATURE\_CLRBHB**, **CPU\_FEATURE\_CSSC**, **CPU\_FEATURE\_DEBUGV8P9**, **CPU\_FEATURE\_DOUBLEFAULT2**, **CPU\_FEATURE\_ECBHB**, **CPU\_FEATURE\_FGT2**, **CPU\_FEATURE\_HAFT**, **CPU\_FEATURE\_LRCPC3**, **CPU\_FEATURE\_MTE4**, **CPU\_FEATURE\_MTE\_ASYNC**, **CPU\_FEATURE\_MTE\_CANONICAL\_TAGS**, **CPU\_FEATURE\_MTE\_NO\_ADDRESS\_TAGS**, **CPU\_FEATURE\_MTE\_PERM**, **CPU\_FEATURE\_MTE\_STORE\_ONLY**, **CPU\_FEATURE\_MTE\_TAGGED\_FAR**, **CPU\_FEATURE\_PFAR**, **CPU\_FEATURE\_PMUV3\_ICNTR**, **CPU\_FEATURE\_PMUV3\_SS**, **CPU\_FEATURE\_PMUV3P9**, **CPU\_FEATURE\_PRFMSLC**, **CPU\_FEATURE\_RASV2**, **CPU\_FEATURE\_RPRFM**, **CPU\_FEATURE\_S1PIE**, **CPU\_FEATURE\_S1POE**, **CPU\_FEATURE\_S2PIE**, **CPU\_FEATURE\_S2POE**, **CPU\_FEATURE\_SPECRES2**, **CPU\_FEATURE\_SPE\_DPFZS**, **CPU\_FEATURE\_SPEV1P4**, **CPU\_FEATURE\_SPMU**, **CPU\_FEATURE\_THE**, **CPU\_FEATURE\_SVE2**, **CPU\_FEATURE\_SVE\_AES**, **CPU\_FEATURE\_SVE\_BITPERM**, **CPU\_FEATURE\_SVE\_PMULL128**, **CPU\_FEATURE\_SVE\_SHA3**, **CPU\_FEATURE\_SVE\_SM4**, **CPU\_FEATURE\_TME**, **CPU\_FEATURE\_TRBE**, **CPU\_FEATURE\_BRBE**, **CPU\_FEATURE\_RME**, **CPU\_FEATURE\_SME**, **CPU\_FEATURE\_SME\_F64F64**, **CPU\_FEATURE\_SME\_FA64**, **CPU\_FEATURE\_SME\_I16I64**, **CPU\_FEATURE\_BRBEV1P1**, **CPU\_FEATURE\_MEC**, **CPU\_FEATURE\_SME2**, **CPU\_FEATURE\_ABLE**, **CPU\_FEATURE\_BWE**, **CPU\_FEATURE\_D128**, **CPU\_FEATURE\_EBEP**, **CPU\_FEATURE\_GCS**, **CPU\_FEATURE\_ITE**, **CPU\_FEATURE\_LSE128**, **CPU\_FEATURE\_LVA3**, **CPU\_FEATURE\_SEBEP**, **CPU\_FEATURE\_SME2P1**, **CPU\_FEATURE\_SME\_F16F16**, **CPU\_FEATURE\_SVE2P1**, **CPU\_FEATURE\_SVE\_B16B16**, **CPU\_FEATURE\_SYSINSTR128**, **CPU\_FEATURE\_SYSREG128**, **CPU\_FEATURE\_TRBE\_EXT**, **CPU\_FEATURE\_ASID2**, **CPU\_FEATURE\_BWE2**, **CPU\_FEATURE\_CPA**, **CPU\_FEATURE\_CPA2**, **CPU\_FEATURE\_E2H0**, **CPU\_FEATURE\_E3DSE**, **CPU\_FEATURE\_ETS3**, **CPU\_FEATURE\_FAMINMAX**, **CPU\_FEATURE\_FGWTE3**, **CPU\_FEATURE\_FP8**, **CPU\_FEATURE\_FP8DOT2**, **CPU\_FEATURE\_FP8DOT4**, **CPU\_FEATURE\_FP8FMA**, **CPU\_FEATURE\_FPMR**, **CPU\_FEATURE\_HACDBS**, **CPU\_FEATURE\_HDBSS**, **CPU\_FEATURE\_LUT**, **CPU\_FEATURE\_PAUTH\_LR**, **CPU\_FEATURE\_RME\_GPC2**, **CPU\_FEATURE\_SME\_F8F16**, **CPU\_FEATURE\_SME\_F8F32**, **CPU\_FEATURE\_SME\_LUTV2**, **CPU\_FEATURE\_SPMU2**, **CPU\_FEATURE\_SSVE\_FP8DOT2**, **CPU\_FEATURE\_SSVE\_FP8DOT4**, **CPU\_FEATURE\_SSVE\_FP8FMA**, **CPU\_FEATURE\_STEP2**, **CPU\_FEATURE\_TLBIW**, **NUM\_CPU\_FEATURES** }\ CPU feature identifiers. enum **cpu\_hint\_t** { **CPU\_HINT\_SSE\_SIZE\_AUTH** = 0, **NUM\_CPU\_HINTS** }\ CPU detection hints identifiers. enum **cpu\_sgx\_feature\_t** { **INTEL\_SGX1**, **INTEL\_SGX2**, **NUM\_SGX\_FEATURES** }\ SGX features flags. enum **cpu\_error\_t** { **ERR\_OK** = 0, **ERR\_NO\_CPUID** = -1, **ERR\_NO\_RDTSC** = -2, **ERR\_NO\_MEM** = -3, **ERR\_OPEN** = -4, **ERR\_BADFMT** = -5, **ERR\_NOT\_IMP** = -6, **ERR\_CPU\_UNKN** = -7, **ERR\_NO\_RDMSR** = -8, **ERR\_NO\_DRIVER** = -9, **ERR\_NO\_PERMS** = -10, **ERR\_EXTRACT** = -11, **ERR\_HANDLE** = -12, **ERR\_INVMSR** = -13, **ERR\_INVCNB** = -14, **ERR\_HANDLE\_R** = -15, **ERR\_INVRANGE** = -16, **ERR\_NOT\_FOUND** = -17, **ERR\_IOCTL** = -18, **ERR\_REQUEST** = -19 }\ Describes common library error codes. enum **cpu\_msrinfo\_request\_t** { **INFO\_MPERF**, **INFO\_APERF**, **INFO\_MIN\_MULTIPLIER**, **INFO\_CUR\_MULTIPLIER**, **INFO\_MAX\_MULTIPLIER**, **INFO\_TEMPERATURE**, **INFO\_THROTTLING**, **INFO\_VOLTAGE**, **INFO\_BCLK**, **INFO\_BUS\_CLOCK** }\ ### Functions int **cpuid\_get\_total\_cpus** (void)\ Returns the total number of logical CPU threads (even if CPUID is not present). int **cpuid\_present** (void)\ Checks if the CPUID instruction is supported. void **cpu\_exec\_cpuid** (uint32\_t eax, uint32\_t \*regs)\ Executes the CPUID instruction. void **cpu\_exec\_cpuid\_ext** (uint32\_t \*regs)\ Executes the CPUID instruction with the given input registers. int **cpuid\_get\_raw\_data** (struct **cpu\_raw\_data\_t** \*data)\ Obtains the raw CPUID data from the current CPU. int **cpuid\_get\_raw\_data\_core** (struct **cpu\_raw\_data\_t** \*data, logical\_cpu\_t logical\_cpu)\ Obtains the raw CPUID data from the specified CPU. int **cpuid\_get\_all\_raw\_data** (struct **cpu\_raw\_data\_array\_t** \*data)\ Obtains the raw CPUID data from all CPUs. int **cpuid\_serialize\_raw\_data** (struct **cpu\_raw\_data\_t** \*data, const char \*filename)\ Writes the raw CPUID data to a text file. int **cpuid\_serialize\_all\_raw\_data** (struct **cpu\_raw\_data\_array\_t** \*data, const char \*filename)\ Writes all the raw CPUID data to a text file. int **cpuid\_deserialize\_raw\_data** (struct **cpu\_raw\_data\_t** \*data, const char \*filename)\ Reads raw CPUID data from file. int **cpuid\_deserialize\_all\_raw\_data** (struct **cpu\_raw\_data\_array\_t** \*data, const char \*filename)\ Reads all raw CPUID data from file. int **cpu\_identify** (struct **cpu\_raw\_data\_t** \*raw, struct **cpu\_id\_t** \*data)\ Identifies the CPU. int **cpu\_identify\_all** (struct **cpu\_raw\_data\_array\_t** \*raw\_array, struct **system\_id\_t** \*system)\ Identifies all the CPUs. int **cpu\_request\_core\_type** (**cpu\_purpose\_t** purpose, struct **cpu\_raw\_data\_array\_t** \*raw\_array, struct **cpu\_id\_t** \*data)\ Identifies a given CPU type. const char \* **cpu\_architecture\_str** (**cpu\_architecture\_t** architecture)\ Returns the short textual representation of a CPU architecture. const char \* **cpu\_feature\_level\_str** (**cpu\_feature\_level\_t** level)\ Returns the short textual representation of a CPU feature level. const char \* **cpu\_purpose\_str** (**cpu\_purpose\_t** purpose)\ Returns the short textual representation of a CPU purpose. char \* **affinity\_mask\_str\_r** (**cpu\_affinity\_mask\_t** \*affinity\_mask, char \*buffer, uint32\_t buffer\_len)\ Returns textual representation of a CPU affinity mask (thread-safe). char \* **affinity\_mask\_str** (**cpu\_affinity\_mask\_t** \*affinity\_mask)\ Returns textual representation of a CPU affinity mask. void **cpu\_rdtsc** (uint64\_t \*result)\ Returns the short textual representation of a CPU flag. void **cpu\_tsc\_mark** (struct **cpu\_mark\_t** \*mark)\ Store TSC and timing info. int **cpu\_clock\_by\_os** (void)\ Calculate TSC and timing difference. int **cpu\_clock\_by\_ic** (int millis, int runs)\ Measure the CPU clock frequency. int **cpu\_clock\_by\_tsc** (struct **cpu\_raw\_data\_t** \*raw)\ Measure the CPU clock frequency using TSC frequency from CPUID. int **cpu\_clock** (void)\ Get the CPU clock frequency (all-in-one method). struct **cpu\_epc\_t** **cpuid\_get\_epc** (int index, const struct **cpu\_raw\_data\_t** \*raw)\ Fetches information about an EPC (Enclave Page Cache) area. const char \* **cpuid\_lib\_version** (void)\ Returns the libcpuid version. libcpuid\_warn\_fn\_t **cpuid\_set\_warn\_function** (libcpuid\_warn\_fn\_t warn\_fun)\ Sets the warning print function. void **cpuid\_set\_verbosiness\_level** (int level)\ Sets the verbosiness level. **cpu\_vendor\_t** **cpuid\_get\_vendor** (void)\ Obtains the CPU vendor from CPUID from the current CPU. **hypervisor\_vendor\_t** **cpuid\_get\_hypervisor** (struct **cpu\_raw\_data\_t** \*raw, struct **cpu\_id\_t** \*data)\ Obtains the hypervisor vendor from CPUID from the current CPU. void **cpuid\_get\_cpu\_list** (**cpu\_vendor\_t** vendor, struct **cpu\_list\_t** \*list)\ Gets a list of all known CPU names from a specific vendor. void **cpuid\_free\_cpu\_list** (struct **cpu\_list\_t** \*list)\ Frees a CPU list. void **cpuid\_free\_raw\_data\_array** (struct **cpu\_raw\_data\_array\_t** \*raw\_array)\ Frees a raw array. void **cpuid\_free\_system\_id** (struct **system\_id\_t** \*system)\ Frees a system ID type. struct msr\_driver\_t \* **cpu\_msr\_driver\_open** (void)\ Starts/opens a driver, needed to read MSRs (Model Specific Registers). struct msr\_driver\_t \* **cpu\_msr\_driver\_open\_core** (unsigned core\_num)\ Similar to **cpu\_msr\_driver\_open**, but accept one parameter. int **cpu\_rdmsr** (struct msr\_driver\_t \*handle, uint32\_t msr\_index, uint64\_t \*result)\ Reads a Model-Specific Register (MSR). int **cpu\_rdmsr\_range** (struct msr\_driver\_t \*handle, uint32\_t msr\_index, uint8\_t highbit, uint8\_t lowbit, uint64\_t \*result)\ Similar to **cpu\_rdmsr**, but extract a range of bits. int **cpu\_msrinfo** (struct msr\_driver\_t \*handle, **cpu\_msrinfo\_request\_t** which)\ Reads extended CPU information from Model-Specific Registers. int **msr\_serialize\_raw\_data** (struct msr\_driver\_t \*handle, const char \*filename)\ Writes the raw MSR data to a text file. int **cpu\_msr\_driver\_close** (struct msr\_driver\_t \*handle)\ Closes an open MSR driver. ## Detailed Description LibCPUID provides CPU identification. ## Enumeration Type Documentation ### enum cpu\_architecture\_t CPU architecture. **Enumerator** - ***ARCHITECTURE\_X86*** x86 CPU - ***ARCHITECTURE\_ARM*** ARM CPU - ***NUM\_CPU\_ARCHITECTURES*** Valid CPU architecture ids: 0..NUM\_CPU\_ARCHITECTURES - 1 ### enum cpu\_error\_t Describes common library error codes. **Enumerator** - ***ERR\_OK*** No error - ***ERR\_NO\_CPUID*** CPUID instruction is not supported - ***ERR\_NO\_RDTSC*** RDTSC instruction is not supported - ***ERR\_NO\_MEM*** Memory allocation failed - ***ERR\_OPEN*** File open operation failed - ***ERR\_BADFMT*** Bad file format - ***ERR\_NOT\_IMP*** Not implemented - ***ERR\_CPU\_UNKN*** Unsupported processor - ***ERR\_NO\_RDMSR*** RDMSR instruction is not supported - ***ERR\_NO\_DRIVER*** RDMSR driver error (generic) - ***ERR\_NO\_PERMS*** No permissions to install RDMSR driver - ***ERR\_EXTRACT*** Cannot extract RDMSR driver (read only media?) - ***ERR\_HANDLE*** Bad handle - ***ERR\_INVMSR*** Invalid MSR - ***ERR\_INVCNB*** Invalid core number - ***ERR\_HANDLE\_R*** Error on handle read - ***ERR\_INVRANGE*** Invalid given range - ***ERR\_NOT\_FOUND*** Requested type not found - ***ERR\_IOCTL*** Error on ioctl - ***ERR\_REQUEST*** Invalid request ### enum cpu\_feature\_level\_t CPU feature level. **Enumerator** - ***FEATURE\_LEVEL\_I386*** i386 - ***FEATURE\_LEVEL\_I486*** i486 - ***FEATURE\_LEVEL\_I586*** i586 - ***FEATURE\_LEVEL\_I686*** i686 - ***FEATURE\_LEVEL\_X86\_64\_V1*** x86-64-v1 - ***FEATURE\_LEVEL\_X86\_64\_V2*** x86-64-v2 - ***FEATURE\_LEVEL\_X86\_64\_V3*** x86-64-v3 - ***FEATURE\_LEVEL\_X86\_64\_V4*** x86-64-v4 - ***FEATURE\_LEVEL\_ARM\_V1*** ARMv1 - ***FEATURE\_LEVEL\_ARM\_V2*** ARMv2 - ***FEATURE\_LEVEL\_ARM\_V3*** ARMv3 - ***FEATURE\_LEVEL\_ARM\_V4*** ARMv4 - ***FEATURE\_LEVEL\_ARM\_V4T*** ARMv4T - ***FEATURE\_LEVEL\_ARM\_V5*** ARMv5 (obsolete) - ***FEATURE\_LEVEL\_ARM\_V5T*** ARMv5T - ***FEATURE\_LEVEL\_ARM\_V5TE*** ARMv5TE - ***FEATURE\_LEVEL\_ARM\_V5TEJ*** ARMv5TEJ - ***FEATURE\_LEVEL\_ARM\_V6*** ARMv6 - ***FEATURE\_LEVEL\_ARM\_V6\_M*** ARMv6-M - ***FEATURE\_LEVEL\_ARM\_V7\_A*** ARMv7-A - ***FEATURE\_LEVEL\_ARM\_V7\_M*** ARMv7-M - ***FEATURE\_LEVEL\_ARM\_V7\_R*** ARMv7-R - ***FEATURE\_LEVEL\_ARM\_V7E\_M*** ARMv7E-M - ***FEATURE\_LEVEL\_ARM\_V8\_0\_A*** ARMv8.0-A - ***FEATURE\_LEVEL\_ARM\_V8\_0\_M*** ARMv8.0-M - ***FEATURE\_LEVEL\_ARM\_V8\_0\_R*** ARMv8.0-R - ***FEATURE\_LEVEL\_ARM\_V8\_1\_A*** ARMv8.1-A - ***FEATURE\_LEVEL\_ARM\_V8\_1\_M*** ARMv8.1-M - ***FEATURE\_LEVEL\_ARM\_V8\_2\_A*** ARMv8.2-A - ***FEATURE\_LEVEL\_ARM\_V8\_3\_A*** ARMv8.3-A - ***FEATURE\_LEVEL\_ARM\_V8\_4\_A*** ARMv8.4-A - ***FEATURE\_LEVEL\_ARM\_V8\_5\_A*** ARMv8.5-A - ***FEATURE\_LEVEL\_ARM\_V8\_6\_A*** ARMv8.6-A - ***FEATURE\_LEVEL\_ARM\_V8\_7\_A*** ARMv8.7-A - ***FEATURE\_LEVEL\_ARM\_V8\_8\_A*** ARMv8.8-A - ***FEATURE\_LEVEL\_ARM\_V8\_9\_A*** ARMv8.9-A - ***FEATURE\_LEVEL\_ARM\_V9\_0\_A*** ARMv9.0-A - ***FEATURE\_LEVEL\_ARM\_V9\_1\_A*** ARMv9.1-A - ***FEATURE\_LEVEL\_ARM\_V9\_2\_A*** ARMv9.2-A - ***FEATURE\_LEVEL\_ARM\_V9\_3\_A*** ARMv9.3-A - ***FEATURE\_LEVEL\_ARM\_V9\_4\_A*** ARMv9.4-A - ***FEATURE\_LEVEL\_ARM\_V9\_5\_A*** ARMv9.5-A - ***NUM\_FEATURE\_LEVELS*** Valid feature level ids: 0..NUM\_FEATURE\_LEVELS - 1 ### enum cpu\_feature\_t CPU feature identifiers. Usage: ``` ... struct cpu_raw_data_t raw; struct cpu_id_t id; if (cpuid_get_raw_data(&raw) == 0 && cpu_identify(&raw, &id) == 0) { if (id.flags[CPU_FEATURE_SSE2]) { // The CPU has SSE2... ... } else { // no SSE2 } } else { // processor cannot be determined. } ``` **Enumerator** - ***CPU\_FEATURE\_FPU*** Floating point unit - ***CPU\_FEATURE\_VME*** Virtual mode extension - ***CPU\_FEATURE\_DE*** Debugging extension - ***CPU\_FEATURE\_PSE*** Page size extension - ***CPU\_FEATURE\_TSC*** Time-stamp counter - ***CPU\_FEATURE\_MSR*** Model-specific regsisters, RDMSR/WRMSR supported - ***CPU\_FEATURE\_PAE*** Physical address extension - ***CPU\_FEATURE\_MCE*** Machine check exception - ***CPU\_FEATURE\_CX8*** CMPXCHG8B instruction supported - ***CPU\_FEATURE\_APIC*** APIC support - ***CPU\_FEATURE\_MTRR*** Memory type range registers - ***CPU\_FEATURE\_SEP*** SYSENTER / SYSEXIT instructions supported - ***CPU\_FEATURE\_PGE*** Page global enable - ***CPU\_FEATURE\_MCA*** Machine check architecture - ***CPU\_FEATURE\_CMOV*** CMOVxx instructions supported - ***CPU\_FEATURE\_PAT*** Page attribute table - ***CPU\_FEATURE\_PSE36*** 36-bit page address extension - ***CPU\_FEATURE\_PN*** Processor serial # implemented (Intel P3 only) - ***CPU\_FEATURE\_CLFLUSH*** CLFLUSH instruction supported - ***CPU\_FEATURE\_DTS*** Debug store supported - ***CPU\_FEATURE\_ACPI*** ACPI support (power states) - ***CPU\_FEATURE\_MMX*** MMX instruction set supported - ***CPU\_FEATURE\_FXSR*** FXSAVE / FXRSTOR supported - ***CPU\_FEATURE\_SSE*** Streaming-SIMD Extensions (SSE) supported - ***CPU\_FEATURE\_SSE2*** SSE2 instructions supported - ***CPU\_FEATURE\_SS*** Self-snoop - ***CPU\_FEATURE\_HT*** Hyper-threading supported (but might be disabled) - ***CPU\_FEATURE\_TM*** Thermal monitor - ***CPU\_FEATURE\_IA64*** IA64 supported (Itanium only) - ***CPU\_FEATURE\_PBE*** Pending-break enable - ***CPU\_FEATURE\_PNI*** PNI (SSE3) instructions supported - ***CPU\_FEATURE\_PCLMUL*** PCLMULQDQ instruction supported - ***CPU\_FEATURE\_DTS64*** 64-bit Debug store supported - ***CPU\_FEATURE\_MONITOR*** MONITOR / MWAIT supported - ***CPU\_FEATURE\_DS\_CPL*** CPL Qualified Debug Store - ***CPU\_FEATURE\_VMX*** Virtualization technology supported - ***CPU\_FEATURE\_SMX*** Safer mode exceptions - ***CPU\_FEATURE\_EST*** Enhanced SpeedStep - ***CPU\_FEATURE\_TM2*** Thermal monitor 2 - ***CPU\_FEATURE\_SSSE3*** SSSE3 instructionss supported (this is different from SSE3!) - ***CPU\_FEATURE\_CID*** Context ID supported - ***CPU\_FEATURE\_CX16*** CMPXCHG16B instruction supported - ***CPU\_FEATURE\_XTPR*** Send Task Priority Messages disable - ***CPU\_FEATURE\_PDCM*** Performance capabilities MSR supported - ***CPU\_FEATURE\_DCA*** Direct cache access supported - ***CPU\_FEATURE\_SSE4\_1*** SSE 4.1 instructions supported - ***CPU\_FEATURE\_SSE4\_2*** SSE 4.2 instructions supported - ***CPU\_FEATURE\_SYSCALL*** SYSCALL / SYSRET instructions supported - ***CPU\_FEATURE\_XD*** Execute disable bit supported - ***CPU\_FEATURE\_MOVBE*** MOVBE instruction supported - ***CPU\_FEATURE\_POPCNT*** POPCNT instruction supported - ***CPU\_FEATURE\_AES*** AES\* instructions supported - ***CPU\_FEATURE\_XSAVE*** XSAVE/XRSTOR/etc instructions supported - ***CPU\_FEATURE\_OSXSAVE*** non-privileged copy of OSXSAVE supported - ***CPU\_FEATURE\_AVX*** Advanced vector extensions supported - ***CPU\_FEATURE\_MMXEXT*** AMD MMX-extended instructions supported - ***CPU\_FEATURE\_3DNOW*** AMD 3DNow! instructions supported - ***CPU\_FEATURE\_3DNOWEXT*** AMD 3DNow! extended instructions supported - ***CPU\_FEATURE\_NX*** No-execute bit supported - ***CPU\_FEATURE\_FXSR\_OPT*** FFXSR: FXSAVE and FXRSTOR optimizations - ***CPU\_FEATURE\_RDTSCP*** RDTSCP instruction supported (AMD-only) - ***CPU\_FEATURE\_LM*** Long mode (x86\_64/EM64T) supported - ***CPU\_FEATURE\_LAHF\_LM*** LAHF/SAHF supported in 64-bit mode - ***CPU\_FEATURE\_CMP\_LEGACY*** core multi-processing legacy mode - ***CPU\_FEATURE\_SVM*** AMD Secure virtual machine - ***CPU\_FEATURE\_ABM*** LZCNT instruction support - ***CPU\_FEATURE\_MISALIGNSSE*** Misaligned SSE supported - ***CPU\_FEATURE\_SSE4A*** SSE 4a from AMD - ***CPU\_FEATURE\_3DNOWPREFETCH*** PREFETCH/PREFETCHW support - ***CPU\_FEATURE\_OSVW*** OS Visible Workaround (AMD) - ***CPU\_FEATURE\_IBS*** Instruction-based sampling - ***CPU\_FEATURE\_SSE5*** SSE 5 instructions supported (deprecated, will never be 1) - ***CPU\_FEATURE\_SKINIT*** SKINIT / STGI supported - ***CPU\_FEATURE\_WDT*** Watchdog timer support - ***CPU\_FEATURE\_TS*** Temperature sensor - ***CPU\_FEATURE\_FID*** Frequency ID control - ***CPU\_FEATURE\_VID*** Voltage ID control - ***CPU\_FEATURE\_TTP*** THERMTRIP - ***CPU\_FEATURE\_TM\_AMD*** AMD-specified hardware thermal control - ***CPU\_FEATURE\_STC*** Software thermal control - ***CPU\_FEATURE\_100MHZSTEPS*** 100 MHz multiplier control - ***CPU\_FEATURE\_HWPSTATE*** Hardware P-state control - ***CPU\_FEATURE\_CONSTANT\_TSC*** TSC ticks at constant rate - ***CPU\_FEATURE\_XOP*** The XOP instruction set (same as the old CPU\_FEATURE\_SSE5) - ***CPU\_FEATURE\_FMA3*** The FMA3 instruction set - ***CPU\_FEATURE\_FMA4*** The FMA4 instruction set - ***CPU\_FEATURE\_TBM*** Trailing bit manipulation instruction support - ***CPU\_FEATURE\_F16C*** 16-bit FP convert instruction support - ***CPU\_FEATURE\_RDRAND*** RdRand instruction - ***CPU\_FEATURE\_X2APIC*** x2APIC, APIC\_BASE.EXTD, MSRs 0000\_0800h...0000\_0BFFh 64-bit ICR (+030h but not +031h), no DFR (+00Eh), SELF\_IPI (+040h) also see standard level 0000\_000Bh - ***CPU\_FEATURE\_CPB*** Core performance boost - ***CPU\_FEATURE\_APERFMPERF*** MPERF/APERF MSRs support - ***CPU\_FEATURE\_PFI*** Processor Feedback Interface support - ***CPU\_FEATURE\_PA*** Processor accumulator - ***CPU\_FEATURE\_AVX2*** AVX2 instructions - ***CPU\_FEATURE\_BMI1*** BMI1 instructions - ***CPU\_FEATURE\_BMI2*** BMI2 instructions - ***CPU\_FEATURE\_HLE*** Hardware Lock Elision prefixes - ***CPU\_FEATURE\_RTM*** Restricted Transactional Memory instructions - ***CPU\_FEATURE\_AVX512F*** AVX-512 Foundation - ***CPU\_FEATURE\_AVX512DQ*** AVX-512 Double/Quad granular insns - ***CPU\_FEATURE\_AVX512PF*** AVX-512 Prefetch - ***CPU\_FEATURE\_AVX512ER*** AVX-512 Exponential/Reciprocal - ***CPU\_FEATURE\_AVX512CD*** AVX-512 Conflict detection - ***CPU\_FEATURE\_SHA\_NI*** SHA-1/SHA-256 instructions - ***CPU\_FEATURE\_AVX512BW*** AVX-512 Byte/Word granular insns - ***CPU\_FEATURE\_AVX512VL*** AVX-512 128/256 vector length extensions - ***CPU\_FEATURE\_SGX*** SGX extensions. Non-autoritative, check cpu\_id\_t::sgx::present to verify presence - ***CPU\_FEATURE\_RDSEED*** RDSEED instruction - ***CPU\_FEATURE\_ADX*** ADX extensions (arbitrary precision) - ***CPU\_FEATURE\_AVX512VNNI*** AVX-512 Vector Neural Network Instructions - ***CPU\_FEATURE\_AVX512VBMI*** AVX-512 Vector Bit ManipulationInstructions (version 1) - ***CPU\_FEATURE\_AVX512VBMI2*** AVX-512 Vector Bit ManipulationInstructions (version 2) - ***CPU\_FEATURE\_HYPERVISOR*** Hypervisor present (always zero on physical CPUs) - ***CPU\_FEATURE\_SWAP*** ARM: Swap instructions in the ARM instruction set - ***CPU\_FEATURE\_THUMB*** ARM: Thumb instruction set support - ***CPU\_FEATURE\_ADVMULTU*** ARM: Advanced unsigned Multiply instructions - ***CPU\_FEATURE\_ADVMULTS*** ARM: Advanced signed Multiply instructions - ***CPU\_FEATURE\_JAZELLE*** ARM: Jazelle extension support - ***CPU\_FEATURE\_DEBUGV6*** ARM: Support for v6 Debug architecture - ***CPU\_FEATURE\_DEBUGV6P1*** ARM: Support for v6.1 Debug architecture - ***CPU\_FEATURE\_THUMB2*** ARM: Thumb-2, instruction set support - ***CPU\_FEATURE\_DEBUGV7*** ARM: Support for v7 Debug architecture - ***CPU\_FEATURE\_DEBUGV7P1*** ARM: Support for v7.1 Debug architecture - ***CPU\_FEATURE\_THUMBEE*** ARM: ThumbEE instruction set support - ***CPU\_FEATURE\_DIVIDE*** ARM: Divide instructions - ***CPU\_FEATURE\_LPAE*** ARM: Large Physical Address Extension - ***CPU\_FEATURE\_PMUV1*** ARM: PMU extension version 1 - ***CPU\_FEATURE\_PMUV2*** ARM: PMU extension version 2 - ***CPU\_FEATURE\_ASID16*** ARM: 16 bit ASID - ***CPU\_FEATURE\_ADVSIMD*** ARM: Advanced SIMD Extension - ***CPU\_FEATURE\_CRC32*** ARM: CRC32 instructions - ***CPU\_FEATURE\_CSV2\_1P1*** ARM: Cache Speculation Variant 2 - ***CPU\_FEATURE\_CSV2\_1P2*** ARM: Cache Speculation Variant 2 version 1.2 - ***CPU\_FEATURE\_CSV2\_2*** ARM: Cache Speculation Variant 2 version 2 - ***CPU\_FEATURE\_CSV2\_3*** ARM: Cache Speculation Variant 2 version 3 - ***CPU\_FEATURE\_DOUBLELOCK*** ARM: Double Lock - ***CPU\_FEATURE\_ETS2*** ARM: Enhanced Translation Synchronization - ***CPU\_FEATURE\_FP*** ARM: Floating Point extensions - ***CPU\_FEATURE\_MIXEDEND*** ARM: Mixed-endian support - ***CPU\_FEATURE\_MIXEDENDEL0*** ARM: Mixed-endian support at EL0 - ***CPU\_FEATURE\_PMULL*** ARM: Advanced SIMD PMULL instructions - ***CPU\_FEATURE\_PMUV3*** ARM: PMU extension version 3 - ***CPU\_FEATURE\_SHA1*** ARM: Advanced SIMD SHA1 instructions - ***CPU\_FEATURE\_SHA256*** ARM: Advanced SIMD SHA256 instructions - ***CPU\_FEATURE\_NTLBPA*** ARM: Intermediate caching of translation table walks - ***CPU\_FEATURE\_HAFDBS*** ARM: Hardware management of the Access flag and dirty state - ***CPU\_FEATURE\_HPDS*** ARM: Hierarchical permission disables in translations tables - ***CPU\_FEATURE\_LOR*** ARM: Limited ordering regions - ***CPU\_FEATURE\_LSE*** ARM: Large System Extensions - ***CPU\_FEATURE\_PAN*** ARM: Privileged access never - ***CPU\_FEATURE\_PMUV3P1*** ARM: Armv8.1 PMU extensions - ***CPU\_FEATURE\_RDM*** ARM: Advanced SIMD rounding double multiply accumulate instructions - ***CPU\_FEATURE\_VHE*** ARM: Virtualization Host Extensions - ***CPU\_FEATURE\_VMID16*** ARM: 16-bit VMID - ***CPU\_FEATURE\_AA32HPD*** ARM: AArch32 Hierarchical permission disables - ***CPU\_FEATURE\_AA32I8MM*** ARM: AArch32 Int8 matrix multiplication instructions - ***CPU\_FEATURE\_DPB*** ARM: DC CVAP instruction - ***CPU\_FEATURE\_DEBUGV8P2*** ARM: Debug v8.2 - ***CPU\_FEATURE\_F32MM*** ARM: Single-precision Matrix Multiplication - ***CPU\_FEATURE\_F64MM*** ARM: Double-precision Matrix Multiplication - ***CPU\_FEATURE\_FP16*** ARM: Half-precision floating-point data processing - ***CPU\_FEATURE\_HPDS2*** ARM: Hierarchical permission disables - ***CPU\_FEATURE\_I8MM*** ARM: AArch64 Int8 matrix multiplication instructions - ***CPU\_FEATURE\_IESB*** ARM: Implicit Error Synchronization event - ***CPU\_FEATURE\_LPA*** ARM: Large PA and IPA support - ***CPU\_FEATURE\_LSMAOC*** ARM: AArch32 Load/Store Multiple instruction atomicity and ordering controls - ***CPU\_FEATURE\_LVA*** ARM: Large VA support - ***CPU\_FEATURE\_PAN2*** ARM: AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN - ***CPU\_FEATURE\_RAS*** ARM: Reliability, Availability and Serviceability (RAS) Extension - ***CPU\_FEATURE\_SHA3*** ARM: Advanced SIMD SHA3 instructions - ***CPU\_FEATURE\_SHA512*** ARM: Advanced SIMD SHA512 instructions - ***CPU\_FEATURE\_SM3*** ARM: Advanced SIMD SM3 instructions - ***CPU\_FEATURE\_SM4*** ARM: Advanced SIMD SM4 instructions - ***CPU\_FEATURE\_SPE*** ARM: Statistical Profiling Extension - ***CPU\_FEATURE\_SVE*** ARM: Scalable Vector Extension - ***CPU\_FEATURE\_TTCNP*** ARM: Translation table Common not private translations - ***CPU\_FEATURE\_UAO*** ARM: Unprivileged Access Override control - ***CPU\_FEATURE\_XNX*** ARM: Translation table stage 2 Unprivileged Execute-never - ***CPU\_FEATURE\_CCIDX*** ARM: Extended cache index - ***CPU\_FEATURE\_CONSTPACFIELD*** ARM: PAC algorithm enhancement - ***CPU\_FEATURE\_EPAC*** ARM: Enhanced pointer authentication - ***CPU\_FEATURE\_FCMA*** ARM: Floating-point complex number instructions - ***CPU\_FEATURE\_FPAC*** ARM: Faulting on AUT\* instructions - ***CPU\_FEATURE\_FPACCOMBINE*** ARM: Faulting on combined pointer authentication instructions - ***CPU\_FEATURE\_JSCVT*** ARM: JavaScript conversion instructions - ***CPU\_FEATURE\_LRCPC*** ARM: Load-Acquire RCpc instructions - ***CPU\_FEATURE\_PACIMP*** ARM: Pointer authentication - IMPLEMENTATION DEFINED algorithm - ***CPU\_FEATURE\_PACQARMA3*** ARM: Pointer authentication - QARMA3 algorithm - ***CPU\_FEATURE\_PACQARMA5*** ARM: Pointer authentication - QARMA5 algorithm - ***CPU\_FEATURE\_PAUTH*** ARM: Pointer authentication - ***CPU\_FEATURE\_SPEV1P1*** ARM: Statistical Profiling Extension version 1 - ***CPU\_FEATURE\_AMUV1*** ARM: Activity Monitors Extension version 1 - ***CPU\_FEATURE\_BBM*** ARM: Translation table break-before-make levels - ***CPU\_FEATURE\_DIT*** ARM: Data Independent Timing instructions - ***CPU\_FEATURE\_DEBUGV8P4*** ARM: Debug v8.4 - ***CPU\_FEATURE\_DOTPROD*** ARM: Advanced SIMD dot product instructions - ***CPU\_FEATURE\_DOUBLEFAULT*** ARM: Double Fault Extension - ***CPU\_FEATURE\_FHM*** ARM: Floating-point half-precision to single-precision multiply-add instructions - ***CPU\_FEATURE\_FLAGM*** ARM: Condition flag manipulation instructions - ***CPU\_FEATURE\_IDST*** ARM: ID space trap handling - ***CPU\_FEATURE\_LRCPC2*** ARM: Load-Acquire RCpc instructions version 2 - ***CPU\_FEATURE\_LSE2*** ARM: Large System Extensions version 2 - ***CPU\_FEATURE\_MPAM*** ARM: Memory Partitioning and Monitoring Extension - ***CPU\_FEATURE\_PMUV3P4*** ARM: Arm8.4 PMU extensions - ***CPU\_FEATURE\_RASV1P1*** ARM: RAS extension v1.1 - ***CPU\_FEATURE\_S2FWB*** ARM: Stage 2 forced Write-Back - ***CPU\_FEATURE\_SEL2*** ARM: Secure EL2 - ***CPU\_FEATURE\_TLBIOS*** ARM: TLB invalidate instructions in Outer Shareable domain - ***CPU\_FEATURE\_TLBIRANGE*** ARM: TLB invalidate range instructions - ***CPU\_FEATURE\_TRF*** ARM: Self-hosted Trace extensions - ***CPU\_FEATURE\_TTL*** ARM: Translation Table Level - ***CPU\_FEATURE\_TTST*** ARM: Small translation tables - ***CPU\_FEATURE\_BTI*** ARM: Branch Target Identification - ***CPU\_FEATURE\_CSV2*** ARM: Cache Speculation Variant 2 - ***CPU\_FEATURE\_CSV3*** ARM: Cache Speculation Variant 3 - ***CPU\_FEATURE\_DPB2*** ARM: DC CVADP instruction - ***CPU\_FEATURE\_E0PD*** ARM: Preventing EL0 access to halves of address maps - ***CPU\_FEATURE\_EVT*** ARM: Enhanced Virtualization Traps - ***CPU\_FEATURE\_EXS*** ARM: Context synchronization and exception handling - ***CPU\_FEATURE\_FRINTTS*** ARM: Floating-point to integer instructions - ***CPU\_FEATURE\_FLAGM2*** ARM: Enhancements to flag manipulation instructions - ***CPU\_FEATURE\_MTE*** ARM: Memory Tagging Extension - ***CPU\_FEATURE\_MTE2*** ARM: Memory Tagging Extension - ***CPU\_FEATURE\_PMUV3P5*** ARM: Arm8.5 PMU extensions - ***CPU\_FEATURE\_RNG*** ARM: Random number generator - ***CPU\_FEATURE\_RNG\_TRAP*** ARM: Trapping support for RNDR/RNDRRS - ***CPU\_FEATURE\_SB*** ARM: Speculation Barrier - ***CPU\_FEATURE\_SPECRES*** ARM: Speculation restriction instructions - ***CPU\_FEATURE\_SSBS*** ARM: Speculative Store Bypass Safe - ***CPU\_FEATURE\_SSBS2*** ARM: MRS and MSR instructions for SSBS version 2 - ***CPU\_FEATURE\_AA32BF16*** ARM: AArch32 BFloat16 instructions - ***CPU\_FEATURE\_AMUV1P1*** ARM: Activity Monitors Extension version 1.1 - ***CPU\_FEATURE\_BF16*** ARM: AArch64 BFloat16 instructions - ***CPU\_FEATURE\_DGH*** ARM: Data Gathering Hint - ***CPU\_FEATURE\_ECV*** ARM: Enhanced Counter Virtualization - ***CPU\_FEATURE\_FGT*** ARM: Fine Grain Traps - ***CPU\_FEATURE\_HPMN0*** ARM: Setting of MDCR\_EL2.HPMN to zero - ***CPU\_FEATURE\_MPAMV0P1*** ARM: Memory Partitioning and Monitoring extension version 0.1 - ***CPU\_FEATURE\_MPAMV1P1*** ARM: Memory Partitioning and Monitoring extension version 1.1 - ***CPU\_FEATURE\_MTPMU*** ARM: Multi-threaded PMU extensions - ***CPU\_FEATURE\_PAUTH2*** ARM: Enhancements to pointer authentication - ***CPU\_FEATURE\_TWED*** ARM: Delayed Trapping of WFE - ***CPU\_FEATURE\_AFP*** ARM: Alternate floating-point behavior - ***CPU\_FEATURE\_EBF16*** ARM: AArch64 Extended BFloat16 behaviors - ***CPU\_FEATURE\_HCX*** ARM: Support for the HCRX\_EL2 register - ***CPU\_FEATURE\_LPA2*** ARM: Larger physical address for 4KB and 16KB translation granules - ***CPU\_FEATURE\_LS64*** ARM: Support for 64-byte loads and stores without status - ***CPU\_FEATURE\_LS64\_ACCDATA*** ARM: Support for 64-byte EL0 stores with status - ***CPU\_FEATURE\_LS64\_V*** ARM: Support for 64-byte stores with status - ***CPU\_FEATURE\_MTE3*** ARM: MTE Asymmetric Fault Handling - ***CPU\_FEATURE\_MTE\_ASYM\_FAULT*** ARM: Memory tagging asymmetric faults - ***CPU\_FEATURE\_PAN3*** ARM: Support for SCTLR\_ELx.EPAN - ***CPU\_FEATURE\_PMUV3P7*** ARM: Armv8.7 PMU extensions - ***CPU\_FEATURE\_RPRES*** ARM: Increased precision of FRECPE and FRSQRTE - ***CPU\_FEATURE\_SPEV1P2*** ARM: Statistical Profiling Extensions version 1.2 - ***CPU\_FEATURE\_WFXT*** ARM: WFE and WFI instructions with timeout - ***CPU\_FEATURE\_XS*** ARM: XS attribute - ***CPU\_FEATURE\_CMOW*** ARM: Control for cache maintenance permission - ***CPU\_FEATURE\_DEBUGV8P8*** ARM: Debug v8.8 - ***CPU\_FEATURE\_HBC*** ARM: Hinted conditional branches - ***CPU\_FEATURE\_MOPS*** ARM: Standardization of memory operations - ***CPU\_FEATURE\_NMI*** ARM: Non-maskable Interrupts - ***CPU\_FEATURE\_PMUV3P8*** ARM: Armv8.8 PMU extensions - ***CPU\_FEATURE\_SCTLR2*** ARM: Extension to SCTLR\_ELx - ***CPU\_FEATURE\_SPEV1P3*** ARM: Statistical Profiling Extensions version 1.3 - ***CPU\_FEATURE\_TCR2*** ARM: Support for TCR2\_ELx - ***CPU\_FEATURE\_TIDCP1*** ARM: EL0 use of IMPLEMENTATION DEFINED functionality - ***CPU\_FEATURE\_ADERR*** ARM: Asynchronous Device Error Exceptions - ***CPU\_FEATURE\_AIE*** ARM: Memory Attribute Index Enhancement - ***CPU\_FEATURE\_ANERR*** ARM: Asynchronous Normal Error Exceptions - ***CPU\_FEATURE\_ATS1A*** ARM: Address Translation operations that ignore stage 1 permissions - ***CPU\_FEATURE\_CLRBHB*** ARM: Support for Clear Branch History instruction - ***CPU\_FEATURE\_CSSC*** ARM: Common Short Sequence Compression instructions - ***CPU\_FEATURE\_DEBUGV8P9*** ARM: Debug v8.9 - ***CPU\_FEATURE\_DOUBLEFAULT2*** ARM: Double Fault Extension v2 - ***CPU\_FEATURE\_ECBHB*** ARM: Exploitative control using branch history information - ***CPU\_FEATURE\_FGT2*** ARM: Fine-grained traps 2 - ***CPU\_FEATURE\_HAFT*** ARM: Hardware managed Access Flag for Table descriptors - ***CPU\_FEATURE\_LRCPC3*** ARM: Load-Acquire RCpc instructions version 3 - ***CPU\_FEATURE\_MTE4*** ARM: Enhanced Memory Tagging Extension - ***CPU\_FEATURE\_MTE\_ASYNC*** ARM: Asynchronous reporting of Tag Check Fault - ***CPU\_FEATURE\_MTE\_CANONICAL\_TAGS*** ARM: Canonical Tag checking for Untagged memory - ***CPU\_FEATURE\_MTE\_NO\_ADDRESS\_TAGS*** ARM: Memory tagging with Address tagging disabled - ***CPU\_FEATURE\_MTE\_PERM*** ARM: Allocation tag access permission - ***CPU\_FEATURE\_MTE\_STORE\_ONLY*** ARM: Store-only Tag Checking - ***CPU\_FEATURE\_MTE\_TAGGED\_FAR*** ARM: FAR\_ELx on a Tag Check Fault - ***CPU\_FEATURE\_PFAR*** ARM: Physical Fault Address Register Extension - ***CPU\_FEATURE\_PMUV3\_ICNTR*** ARM: Fixed-function instruction counter - ***CPU\_FEATURE\_PMUV3\_SS*** ARM: PMU Snapshot extension - ***CPU\_FEATURE\_PMUV3P9*** ARM: Armv8.9 PMU extensions - ***CPU\_FEATURE\_PRFMSLC*** ARM: SLC target support for PRFM instructions - ***CPU\_FEATURE\_RASV2*** ARM: RAS Extension v2 - ***CPU\_FEATURE\_RPRFM*** ARM: Support for Range Prefetch Memory instruction - ***CPU\_FEATURE\_S1PIE*** ARM: Stage 1 permission indirections - ***CPU\_FEATURE\_S1POE*** ARM: Stage 1 permission overlays - ***CPU\_FEATURE\_S2PIE*** ARM: Stage 2 permission indirections - ***CPU\_FEATURE\_S2POE*** ARM: Stage 2 permission overlays - ***CPU\_FEATURE\_SPECRES2*** ARM: Enhanced speculation restriction instructions - ***CPU\_FEATURE\_SPE\_DPFZS*** ARM: Disable Cycle Counter on SPE Freeze - ***CPU\_FEATURE\_SPEV1P4*** ARM: Statistical Profiling Extension version 1.4 - ***CPU\_FEATURE\_SPMU*** ARM: System Performance Monitors Extension - ***CPU\_FEATURE\_THE*** ARM: Translation Hardening Extension - ***CPU\_FEATURE\_SVE2*** ARM: Scalable Vector Extension version 2 - ***CPU\_FEATURE\_SVE\_AES*** ARM: Scalable Vector AES instructions - ***CPU\_FEATURE\_SVE\_BITPERM*** ARM: Scalable Vector Bit Permutes instructions - ***CPU\_FEATURE\_SVE\_PMULL128*** ARM: SVE single-vector Advanced Encryption Standard and 128-bit polynomial multiply long instructions - ***CPU\_FEATURE\_SVE\_SHA3*** ARM: Scalable Vector SHA3 instructions - ***CPU\_FEATURE\_SVE\_SM4*** ARM: Scalable Vector SM4 instructions - ***CPU\_FEATURE\_TME*** ARM: Transactional Memory Extension - ***CPU\_FEATURE\_TRBE*** ARM: Trace Buffer Extension - ***CPU\_FEATURE\_BRBE*** ARM: Branch Record Buffer Extension - ***CPU\_FEATURE\_RME*** ARM: Realm Management Extension - ***CPU\_FEATURE\_SME*** ARM: Scalable Matrix Extension - ***CPU\_FEATURE\_SME\_F64F64*** ARM: Double-precision floating-point outer product instructions - ***CPU\_FEATURE\_SME\_FA64*** ARM: Full A64 instruction set support in Streaming SVE mode - ***CPU\_FEATURE\_SME\_I16I64*** ARM: 16-bit to 64-bit integer widening outer product instructions - ***CPU\_FEATURE\_BRBEV1P1*** ARM: Branch Record Buffer Extension version 1.1 - ***CPU\_FEATURE\_MEC*** ARM: Memory Encryption Contexts - ***CPU\_FEATURE\_SME2*** ARM: Scalable Matrix Extensions version 2 - ***CPU\_FEATURE\_ABLE*** ARM: Address Breakpoint Linking Extension - ***CPU\_FEATURE\_BWE*** ARM: Breakpoint and watchpoint enhancements - ***CPU\_FEATURE\_D128*** ARM: 128-bit Translation Tables, 56 bit PA - ***CPU\_FEATURE\_EBEP*** ARM: Exception-based Event Profiling - ***CPU\_FEATURE\_GCS*** ARM: Guarded Control Stack Extension - ***CPU\_FEATURE\_ITE*** ARM: Instrumentation Trace Extension - ***CPU\_FEATURE\_LSE128*** ARM: 128-bit Atomics - ***CPU\_FEATURE\_LVA3*** ARM: 56-bit VA - ***CPU\_FEATURE\_SEBEP*** ARM: Synchronous Exception-based Event Profiling - ***CPU\_FEATURE\_SME2P1*** ARM: Scalable Matrix Extension version 2.1 - ***CPU\_FEATURE\_SME\_F16F16*** ARM: Non-widening half-precision FP16 to FP16 arithmetic for SME2 - ***CPU\_FEATURE\_SVE2P1*** ARM: Scalable Vector Extensions version 2.1 - ***CPU\_FEATURE\_SVE\_B16B16*** ARM: Non-widening BFloat16 to BFloat16 arithmetic for SVE2 and SME2 - ***CPU\_FEATURE\_SYSINSTR128*** ARM: 128-bit System instructions - ***CPU\_FEATURE\_SYSREG128*** ARM: 128-bit System registers - ***CPU\_FEATURE\_TRBE\_EXT*** ARM: Trace Buffer external mode - ***CPU\_FEATURE\_ASID2*** ARM: Support for concurrent use of two ASIDs - ***CPU\_FEATURE\_BWE2*** ARM: Breakpoint and watchpoint enhancements 2 - ***CPU\_FEATURE\_CPA*** ARM: Instruction-only Checked Pointer Arithmetic - ***CPU\_FEATURE\_CPA2*** ARM: Checked Pointer Arithmetic - ***CPU\_FEATURE\_E2H0*** ARM: Programming of HCR\_EL2.E2H. - ***CPU\_FEATURE\_E3DSE*** ARM: Delegated SError exception injection - ***CPU\_FEATURE\_ETS3*** ARM: Enhanced Translation Synchronization - ***CPU\_FEATURE\_FAMINMAX*** ARM: Floating-point maximum and minimum absolute value instructions - ***CPU\_FEATURE\_FGWTE3*** ARM: Fine-Grained Write Trap EL3 - ***CPU\_FEATURE\_FP8*** ARM: FP8 convert instructions - ***CPU\_FEATURE\_FP8DOT2*** ARM: FP8 2-way dot product to half-precision instructions - ***CPU\_FEATURE\_FP8DOT4*** ARM: FP8 4-way dot product to single-precision instructions - ***CPU\_FEATURE\_FP8FMA*** ARM: FP8 multiply-accumulate to half-precision and single-precision instructions - ***CPU\_FEATURE\_FPMR*** ARM: Floating-point Mode Register - ***CPU\_FEATURE\_HACDBS*** ARM: Hardware accelerator for cleaning Dirty state - ***CPU\_FEATURE\_HDBSS*** ARM: Hardware Dirty state tracking structure - ***CPU\_FEATURE\_LUT*** ARM: Lookup table instructions with 2-bit and 4-bit indices - ***CPU\_FEATURE\_PAUTH\_LR*** ARM: Pointer authentication instructions that allow signing of LR using SP and PC as diversifiers - ***CPU\_FEATURE\_RME\_GPC2*** ARM: RME Granule Protection Check 2 Extension - ***CPU\_FEATURE\_SME\_F8F16*** ARM: SME2 ZA-targeting FP8 multiply-accumulate, dot product, and outer product to half-precision instructions - ***CPU\_FEATURE\_SME\_F8F32*** ARM: SME2 ZA-targeting FP8 multiply-accumulate, dot product, and outer product to single-precision instructions - ***CPU\_FEATURE\_SME\_LUTV2*** ARM: Lookup table instructions with 4-bit indices and 8-bit elements - ***CPU\_FEATURE\_SPMU2*** ARM: System Performance Monitors Extension version 2 - ***CPU\_FEATURE\_SSVE\_FP8DOT2*** ARM: SVE FP8 2-way dot product to half-precision instructions in Streaming SVE mode - ***CPU\_FEATURE\_SSVE\_FP8DOT4*** ARM: SVE2 FP8 4-way dot product to single-precision instructions in Streaming SVE mode - ***CPU\_FEATURE\_SSVE\_FP8FMA*** ARM: SVE2 FP8 multiply-accumulate to half-precision and single-precision instructions in Streaming SVE mode - ***CPU\_FEATURE\_STEP2*** ARM: Enhanced Software Step Extension - ***CPU\_FEATURE\_TLBIW*** ARM: TLBI VMALL for Dirty state ### enum cpu\_hint\_t CPU detection hints identifiers. Usage: similar to the flags usage **Enumerator** - ***CPU\_HINT\_SSE\_SIZE\_AUTH*** SSE unit size is authoritative (not only a Family/Model guesswork, but based on an actual CPUID bit) ### enum cpu\_msrinfo\_request\_t **Enumerator** - ***INFO\_MPERF*** Maximum performance frequency clock. This is a counter, which increments as a proportion of the actual processor speed. - ***INFO\_APERF*** Actual performance frequency clock. This accumulates the core clock counts when the core is active. - ***INFO\_MIN\_MULTIPLIER*** Minimum CPU:FSB ratio for this CPU, multiplied by 100. - ***INFO\_CUR\_MULTIPLIER*** Current CPU:FSB ratio, multiplied by 100. e.g., a CPU:FSB value of 18.5 reads as "1850". - ***INFO\_MAX\_MULTIPLIER*** Maximum CPU:FSB ratio for this CPU, multiplied by 100. - ***INFO\_TEMPERATURE*** The current core temperature in Celsius. - ***INFO\_THROTTLING*** 1 if the current logical processor is throttling. 0 if it is running normally. - ***INFO\_VOLTAGE*** The current core voltage in Volt, multiplied by 100. - ***INFO\_BCLK*** See **INFO\_BUS\_CLOCK**. - ***INFO\_BUS\_CLOCK*** The main bus clock in MHz, e.g., FSB/QPI/DMI/HT base clock, multiplied by 100. ### enum cpu\_purpose\_t CPU purpose. **Enumerator** - ***PURPOSE\_GENERAL*** general purpose CPU - ***PURPOSE\_PERFORMANCE*** performance CPU - ***PURPOSE\_EFFICIENCY*** efficiency CPU - ***PURPOSE\_LP\_EFFICIENCY*** low-power efficiency CPU - ***PURPOSE\_U\_PERFORMANCE*** ultimate performance CPU - ***NUM\_CPU\_PURPOSES*** Valid CPU purpose ids: 0..NUM\_CPU\_PURPOSES - 1 ### enum cpu\_sgx\_feature\_t SGX features flags. **See also** **cpu\_sgx\_t** Usage: ``` ... struct cpu_raw_data_t raw; struct cpu_id_t id; if (cpuid_get_raw_data(&raw) == 0 && cpu_identify(&raw, &id) == 0 && id.sgx.present) { if (id.sgx.flags[INTEL_SGX1]) // The CPU has SGX1 instructions support... ... } else { // no SGX } } else { // processor cannot be determined. } ``` **Enumerator** - ***INTEL\_SGX1*** SGX1 instructions support - ***INTEL\_SGX2*** SGX2 instructions support ### enum cpu\_vendor\_t CPU vendor, as guessed from the Vendor String. **Enumerator** - ***VENDOR\_INTEL*** Intel CPU - ***VENDOR\_AMD*** AMD CPU - ***VENDOR\_CYRIX*** Cyrix CPU - ***VENDOR\_NEXGEN*** NexGen CPU - ***VENDOR\_TRANSMETA*** Transmeta CPU - ***VENDOR\_UMC*** x86 CPU by UMC - ***VENDOR\_CENTAUR*** x86 CPU by IDT - ***VENDOR\_RISE*** x86 CPU by Rise Technology - ***VENDOR\_SIS*** x86 CPU by SiS - ***VENDOR\_NSC*** x86 CPU by National Semiconductor - ***VENDOR\_HYGON*** Hygon CPU - ***VENDOR\_ARM*** ARM CPU - ***VENDOR\_BROADCOM*** Broadcom Corporation CPU - ***VENDOR\_CAVIUM*** Cavium Inc. CPU - ***VENDOR\_DEC*** Digital Equipment Corporation CPU - ***VENDOR\_FUJITSU*** Fujitsu Ltd. CPU - ***VENDOR\_HISILICON*** HiSilicon Technology Co., Ltd. CPU - ***VENDOR\_INFINEON*** Infineon Technologies AG CPU - ***VENDOR\_FREESCALE*** Motorola or Freescale Semiconductor Inc. CPU - ***VENDOR\_NVIDIA*** NVIDIA Corporation CPU - ***VENDOR\_APM*** Applied Micro Circuits Corporation CPU - ***VENDOR\_QUALCOMM*** Qualcomm Inc. CPU - ***VENDOR\_SAMSUNG*** Samsung Group CPU - ***VENDOR\_MARVELL*** Marvell International Ltd. CPU - ***VENDOR\_APPLE*** Apple Inc. CPU - ***VENDOR\_FARADAY*** Faraday Technology CPU - ***VENDOR\_MICROSOFT*** Microsoft Corporation CPU - ***VENDOR\_PHYTIUM*** Phytium Technology Co., Ltd CPU - ***VENDOR\_AMPERE*** Ampere Computing CPU - ***NUM\_CPU\_VENDORS*** Valid CPU vendor ids: 0..NUM\_CPU\_VENDORS - 1 ### enum hypervisor\_vendor\_t Hypervisor vendor, as guessed from the CPU\_FEATURE\_HYPERVISOR flag. **Enumerator** - ***HYPERVISOR\_NONE*** no hypervisor - ***HYPERVISOR\_BHYVE*** FreeBSD bhyve hypervisor - ***HYPERVISOR\_HYPERV*** Microsoft Hyper-V or Windows Virtual PC hypervisor - ***HYPERVISOR\_KVM*** KVM hypervisor - ***HYPERVISOR\_PARALLELS*** Parallels hypervisor - ***HYPERVISOR\_QEMU*** QEMU hypervisor - ***HYPERVISOR\_VIRTUALBOX*** VirtualBox hypervisor - ***HYPERVISOR\_VMWARE*** VMware hypervisor - ***HYPERVISOR\_XEN*** Xen hypervisor - ***NUM\_HYPERVISOR\_VENDORS*** Valid hypervisor vendor ids: 0..NUM\_HYPERVISOR\_VENDORS - 1 ## Function Documentation ### char \* affinity\_mask\_str (cpu\_affinity\_mask\_t \* affinity\_mask) Returns textual representation of a CPU affinity mask. **Parameters** *affinity\_mask* - the affinity mask (in hexadecimal), whose textual representation is wanted. **Note** This function is not thread-safe **Returns** a string like "0000FFFF", "00FF0000", etc. References **affinity\_mask\_str()**. Referenced by **affinity\_mask\_str()**. ### char \* affinity\_mask\_str\_r (cpu\_affinity\_mask\_t \* affinity\_mask, char \* buffer, uint32\_t buffer\_len) Returns textual representation of a CPU affinity mask (thread-safe). **Parameters** *affinity\_mask* - Input - the affinity mask (in hexadecimal), whose textual representation is wanted. \ *buffer* - Output - an allocated string where to store the textual representation, like "0000FFFF", "00FF0000", etc. \ *buffer\_len* - Input - the size of buffer. **Returns** a pointer on buffer References **affinity\_mask\_str\_r()**. Referenced by **affinity\_mask\_str\_r()**. ### const char \* cpu\_architecture\_str (cpu\_architecture\_t architecture) Returns the short textual representation of a CPU architecture. **Parameters** *architecture* - the architecture, whose textual representation is wanted. **Returns** a constant string like "x86", "ARM", etc. References **cpu\_architecture\_str()**. Referenced by **cpu\_architecture\_str()**. ### int cpu\_clock (void ) Get the CPU clock frequency (all-in-one method). This is an all-in-one method for getting the CPU clock frequency. It tries to use the OS for that. If the OS doesn't have this info, it uses cpu\_clock\_measure with 200ms time interval and quadruple checking. **Returns** the CPU clock frequency in MHz. If every possible method fails, the result is -1. References **cpu\_clock()**. Referenced by **cpu\_clock()**. ### int cpu\_clock\_by\_ic (int millis, int runs) Measure the CPU clock frequency. **Parameters** *millis* - How much time to waste in the busy-wait cycle. In millisecs. Useful values 10 - 1000 \ *quad\_check* - Do a more thorough measurement if nonzero (see the explanation). The function performs a busy-wait cycle for the given time and calculates the CPU frequency by the difference of the TSC values. The accuracy of the calculation depends on the length of the busy-wait cycle: more is better, but 100ms should be enough for most purposes. While this will calculate the CPU frequency correctly in most cases, there are several reasons why it might be incorrect:\ i) RDTSC doesn't guarantee it will run at the same clock as the CPU. Apparently there aren't CPUs at the moment, but still, there's no guarantee.\ \ ii) The CPU might be in a low-frequency power saving mode, and the CPU might be switched to higher frequency at any time. If this happens during the measurement, the result can be anywhere between the low and high frequencies. Also, if you're interested in the high frequency value only, this function might return the low one instead.\ \ iii) On SMP systems exhibiting TSC drift (see **cpu\_rdtsc**) the quad\_check option will run four consecutive measurements and then return the average of the two most-consistent results. The total runtime of the function will still be \`millis' - consider using a bit more time for the timing interval. Finally, for benchmarking / CPU intensive applications, the best strategy is to use the **cpu\_tsc\_mark()** / cpu\_tsc\_unmark() / cpu\_clock\_by\_mark() method. Begin by mark()-ing about one second after application startup (allowing the power-saving manager to kick in and rise the frequency during that time), then unmark() just before application finishing. The result will most acurately represent at what frequency your app was running. **Returns** the CPU clock frequency in MHz (within some measurement error margin). If RDTSC is not supported, the result is -1. \*/ int cpu\_clock\_measure(int millis, int quad\_check); /\*\* Measure the CPU clock frequency using instruction-counting **Parameters** *millis* - how much time to allocate for each run, in milliseconds \ *runs* - how many runs to perform The function performs a busy-wait cycle using a known number of "heavy" (SSE) instructions. These instructions run at (more or less guaranteed) 1 IPC rate, so by running a busy loop for a fixed amount of time, and measuring the amount of instructions done, the CPU clock is accurately measured. Of course, this function is still affected by the power-saving schemes, so the warnings as of cpu\_clock\_measure() still apply. However, this function is immune to problems with detection, related to the Intel Nehalem's "Turbo" mode, where the internal clock is raised, but the RDTSC rate is unaffected. The function will run for about (millis \* runs) milliseconds. You can make only a single busy-wait run (runs == 1); however, this can be affected by task scheduling (which will break the counting), so allowing more than one run is recommended. As run length is not imperative for accurate readings (e.g., 50ms is sufficient), you can afford a lot of short runs, e.g. 10 runs of 50ms or 20 runs of 25ms. Recommended values - millis = 50, runs = 4. For more robustness, increase the number of runs. NOTE: on Bulldozer and later CPUs, the busy-wait cycle runs at 1.4 IPC, thus the results are skewed. This is corrected internally by dividing the resulting value by 1.4. However, this only occurs if the thread is executed on a single CMT module - if there are other threads competing for resources, the results are unpredictable. Make sure you run **cpu\_clock\_by\_ic()** on a CPU that is free from competing threads, or if there are such threads, they shouldn't exceed the number of modules. On a Bulldozer X8, that means 4 threads. **Returns** the CPU clock frequency in MHz (within some measurement error margin). If SSE is not supported, the result is -1. If the input parameters are incorrect, or some other internal fault is detected, the result is -2. References **cpu\_clock\_by\_ic()**. Referenced by **cpu\_clock\_by\_ic()**. ### int cpu\_clock\_by\_os (void ) Calculate TSC and timing difference. **Parameters** *mark* - input/output: a pointer to a **cpu\_mark\_t** structure, which has already been initialized by cpu\_tsc\_mark. The difference in TSC and time will be written here. This function calculates the TSC and time difference, by obtaining the current TSC and timing values and subtracting the contents of the \`mark' structure from them. Results are written in the same structure. Example: ``` ... struct cpu_mark_t mark; cpu_tsc_mark(&mark); foo(); cpu_tsc_unmark(&mark); printf("Foo finished. Executed in %llu cycles and %llu usecs\n", mark.tsc, mark.sys_clock); ... ``` \*/ void cpu\_tsc\_unmark(struct cpu\_mark\_t\* mark); /\*\* Calculates the CPU clock **Parameters** *mark* - pointer to a **cpu\_mark\_t** structure, which has been initialized with cpu\_tsc\_mark and later \`stopped' with cpu\_tsc\_unmark. **Note** For reliable results, the marked time interval should be at least about 10 ms. **Returns** the CPU clock frequency, in MHz. Due to measurement error, it will differ from the true value in a few least-significant bits. Accuracy depends on the timing interval - the more, the better. If the timing interval is insufficient, the result is -1. Also, see the comment on cpu\_clock\_measure for additional issues and pitfalls in using RDTSC for CPU frequency measurements. \*/ int cpu\_clock\_by\_mark(struct cpu\_mark\_t\* mark); /\*\* Returns the CPU clock, as reported by the OS This function uses OS-specific functions to obtain the CPU clock. It may differ from the true clock for several reasons:\ i) The CPU might be in some power saving state, while the OS reports its full-power frequency, or vice-versa.\ \ ii) In some cases you can raise or lower the CPU frequency with overclocking utilities and the OS will not notice. **Returns** the CPU clock frequency in MHz. If the OS is not (yet) supported or lacks the necessary reporting machinery, the return value is -1 References **cpu\_clock\_by\_os()**. Referenced by **cpu\_clock\_by\_os()**. ### int cpu\_clock\_by\_tsc (struct cpu\_raw\_data\_t \* raw) Measure the CPU clock frequency using TSC frequency from CPUID. **Parameters** *raw* - Optional input - a pointer to the raw CPUID data, which is obtained either by cpuid\_get\_raw\_data or cpuid\_deserialize\_raw\_data. Can also be NULL, in which case the functions calls cpuid\_get\_raw\_data itself. The function read Time Stamp Counter and Nominal Core Crystal Clock Information Leaf from CPUID. It determines the processor base frequency. NOTE: only x86 Intel CPUs since Skylake (6th generation of Intel Core processors) are supported. Other vendors do not support this feature. **Returns** the CPU clock frequency in MHz. If TSC frequency is not supported, the result is -1. If the input parameters are incorrect, or some other internal fault is detected, the result is -2. References **cpu\_clock\_by\_tsc()**. Referenced by **cpu\_clock\_by\_tsc()**. ### void cpu\_exec\_cpuid (uint32\_t eax, uint32\_t \* regs) Executes the CPUID instruction. **Parameters** *eax* - the value of the EAX register when executing CPUID \ *regs* - the results will be stored here. regs\[0\] = EAX, regs\[1\] = EBX, ... **Note** CPUID will be executed with EAX set to the given value and EBX, ECX, EDX set to zero. References **cpu\_exec\_cpuid()**. Referenced by **cpu\_exec\_cpuid()**. ### void cpu\_exec\_cpuid\_ext (uint32\_t \* regs) Executes the CPUID instruction with the given input registers. **Note** This is just a bit more generic version of cpu\_exec\_cpuid - it allows you to control all the registers. **Parameters** *regs* - Input/output. Prior to executing CPUID, EAX, EBX, ECX and EDX will be set to regs\[0\], regs\[1\], regs\[2\] and regs\[3\]. After CPUID, this array will contain the results. References **cpu\_exec\_cpuid\_ext()**. Referenced by **cpu\_exec\_cpuid\_ext()**. ### const char \* cpu\_feature\_level\_str (cpu\_feature\_level\_t level) Returns the short textual representation of a CPU feature level. **Parameters** *level* - the feature level, whose textual representation is wanted. **Returns** a constant string like "ARMv8.0-A", "ARMv9.4-A", etc. References **cpu\_feature\_level\_str()**. Referenced by **cpu\_feature\_level\_str()**. ### int cpu\_identify (struct cpu\_raw\_data\_t \* raw, struct cpu\_id\_t \* data) Identifies the CPU. **Parameters** *raw* - Input - a pointer to the raw CPUID data, which is obtained either by cpuid\_get\_raw\_data or cpuid\_deserialize\_raw\_data. Can also be NULL, in which case the functions calls cpuid\_get\_raw\_data itself. \ *data* - Output - the decoded CPU features/info is written here. **Note** The function will not fail, even if some of the information cannot be obtained. Even when the CPU is new and thus unknown to libcpuid, some generic info, such as "AMD K9 family CPU" will be written to data.cpu\_codename, and most other things, such as the CPU flags, cache sizes, etc. should be detected correctly anyway. However, the function CAN fail, if the CPU is completely alien to libcpuid. While **cpu\_identify()** and **cpuid\_get\_raw\_data()** are fast for most purposes, running them several thousand times per second can hamper performance significantly. Specifically, avoid writing "cpu feature checker" wrapping function, which calls cpu\_identify and returns the value of some flag, if that function is going to be called frequently. **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpu\_identify()**. Referenced by **cpu\_identify()**. ### int cpu\_identify\_all (struct cpu\_raw\_data\_array\_t \* raw\_array, struct system\_id\_t \* system) Identifies all the CPUs. **Parameters** *raw\_array* - Input - a pointer to the array of raw CPUID data, which is obtained either by cpuid\_get\_all\_raw\_data or cpuid\_deserialize\_all\_raw\_data. Can also be NULL, in which case the functions calls cpuid\_get\_all\_raw\_data itself. \ *system* - Output - the decoded CPU features/info is written here for each CPU type. **Note** The function is similar to cpu\_identify. Refer to cpu\_identify notes. As the memory is dynamically allocated, be sure to call **cpuid\_free\_raw\_data\_array()** and **cpuid\_free\_system\_id()** after you're done with the data **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpu\_identify\_all()**. Referenced by **cpu\_identify\_all()**. ### int cpu\_msr\_driver\_close (struct msr\_driver\_t \* handle) Closes an open MSR driver. This function unloads the MSR driver opened by cpu\_msr\_driver\_open and frees any resources associated with it. **Parameters** *handle* - a handle to the MSR reader driver, as created by cpu\_msr\_driver\_open **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpu\_msr\_driver\_close()**. Referenced by **cpu\_msr\_driver\_close()**. ### struct msr\_driver\_t \* cpu\_msr\_driver\_open (void ) Starts/opens a driver, needed to read MSRs (Model Specific Registers). On systems that support it, this function will create a temporary system driver, that has privileges to execute the RDMSR instruction. After the driver is created, you can read MSRs by calling **cpu\_rdmsr** **Returns** a handle to the driver on success, and NULL on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpu\_msr\_driver\_open()**. Referenced by **cpu\_msr\_driver\_open()**. ### struct msr\_driver\_t \* cpu\_msr\_driver\_open\_core (unsigned core\_num) Similar to **cpu\_msr\_driver\_open**, but accept one parameter. This function works on certain operating systems (GNU/Linux, FreeBSD) **Parameters** *core\_num* specify the core number for MSR. The first core number is 0. The last core number is **cpuid\_get\_total\_cpus** - 1. **Returns** a handle to the driver on success, and NULL on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpu\_msr\_driver\_open\_core()**. Referenced by **cpu\_msr\_driver\_open\_core()**. ### int cpu\_msrinfo (struct msr\_driver\_t \* handle, cpu\_msrinfo\_request\_t which) Reads extended CPU information from Model-Specific Registers. **Parameters** *handle* - a handle to an open MSR driver, **See also** **cpu\_msr\_driver\_open** **Parameters** *which* - which info field should be returned. A list of available information entities is listed in the **cpu\_msrinfo\_request\_t** enum. **Return values** *-* if the requested information is available for the current processor model, the respective value is returned. if no information is available, or the CPU doesn't support the query, the special value CPU\_INVALID\_VALUE is returned **Note** This function is not MT-safe. If you intend to call it from multiple threads, guard it through a mutex or a similar primitive. References **cpu\_msrinfo()**. Referenced by **cpu\_msrinfo()**. ### const char \* cpu\_purpose\_str (cpu\_purpose\_t purpose) Returns the short textual representation of a CPU purpose. **Parameters** *purpose* - the purpose, whose textual representation is wanted. **Returns** a constant string like "general", "performance", "efficiency", etc. References **cpu\_purpose\_str()**. Referenced by **cpu\_purpose\_str()**. ### int cpu\_rdmsr (struct msr\_driver\_t \* handle, uint32\_t msr\_index, uint64\_t \* result) Reads a Model-Specific Register (MSR). If the CPU has MSRs (as indicated by the CPU\_FEATURE\_MSR flag), you can read a MSR with the given index by calling this function. There are several prerequisites you must do before reading MSRs: 1) You must ensure the CPU has RDMSR. Check the CPU\_FEATURE\_MSR flag in **cpu\_id\_t::flags** 2) You must ensure that the CPU implements the specific MSR you intend to read. 3) You must open a MSR-reader driver. RDMSR is a privileged instruction and needs ring-0 access in order to work. This temporary driver is created by calling **cpu\_msr\_driver\_open** **Parameters** *handle* - a handle to the MSR reader driver, as created by cpu\_msr\_driver\_open \ *msr\_index* - the numeric ID of the MSR you want to read \ *result* - a pointer to a 64-bit integer, where the MSR value is stored **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpu\_rdmsr()**. Referenced by **cpu\_rdmsr()**. ### int cpu\_rdmsr\_range (struct msr\_driver\_t \* handle, uint32\_t msr\_index, uint8\_t highbit, uint8\_t lowbit, uint64\_t \* result) Similar to **cpu\_rdmsr**, but extract a range of bits. **Parameters** *handle* - a handle to the MSR reader driver, as created by cpu\_msr\_driver\_open \ *msr\_index* - the numeric ID of the MSR you want to read \ *highbit* - the high bit in range, must be inferior to 64 \ *lowbit* - the low bit in range, must be equal or superior to 0 \ *result* - a pointer to a 64-bit integer, where the MSR value is stored **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpu\_rdmsr\_range()**. Referenced by **cpu\_rdmsr\_range()**. ### void cpu\_rdtsc (uint64\_t \* result) Returns the short textual representation of a CPU flag. **Parameters** *feature* - the feature, whose textual representation is wanted. **Returns** a constant string like "fpu", "tsc", "sse2", etc. **Note** the names of the returned flags are compatible with those from /proc/cpuinfo in Linux, with the exception of \`tm\_amd' \*/ const char\* cpu\_feature\_str(cpu\_feature\_t feature); /\*\* Returns textual description of the last error libcpuid stores an \`errno'-style error status, whose description can be obtained with this function. **Note** This function is not thread-safe **See also** **cpu\_error\_t** \*/ const char\* cpuid\_error(void); /\*\* Executes RDTSC The RDTSC (ReaD Time Stamp Counter) instruction gives access to an internal 64-bit counter, which usually increments at each clock cycle. This can be used for various timing routines, and as a very precise clock source. It is set to zero on system startup. Beware that may not increment at the same frequency as the CPU. Consecutive calls of RDTSC are, however, guaranteed to return monotonically-increasing values. **Parameters** *result* - a pointer to a 64-bit unsigned integer, where the TSC value will be stored **Note** If 100% compatibility is a concern, you must first check if the RDTSC instruction is present (if it is not, your program will crash with "invalid opcode" exception). Only some very old processors (i486, early AMD K5 and some Cyrix CPUs) lack that instruction - they should have become exceedingly rare these days. To verify RDTSC presence, run **cpu\_identify()** and check flags\[CPU\_FEATURE\_TSC\]. The monotonically increasing nature of the TSC may be violated on SMP systems, if their TSC clocks run at different rate. If the OS doesn't account for that, the TSC drift may become arbitrary large. References **cpu\_rdtsc()**. Referenced by **cpu\_rdtsc()**. ### int cpu\_request\_core\_type (cpu\_purpose\_t purpose, struct cpu\_raw\_data\_array\_t \* raw\_array, struct cpu\_id\_t \* data) Identifies a given CPU type. **Parameters** *purpose* - Input - a **cpu\_purpose\_t** to request \ *raw\_array* - Optional input - a pointer to the array of raw CPUID data, which is obtained either by cpuid\_get\_all\_raw\_data or cpuid\_deserialize\_all\_raw\_data. Can also be NULL, in which case the functions calls cpuid\_get\_all\_raw\_data itself. \ *data* - Output - the decoded CPU features/info is written here. **Returns** zero if successful, and some negative number on error (like ERR\_NOT\_FOUND if CPU type not found). The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpu\_request\_core\_type()**. Referenced by **cpu\_request\_core\_type()**. ### void cpu\_tsc\_mark (struct cpu\_mark\_t \* mark) Store TSC and timing info. This function stores the current TSC value and current time info from a precise OS-specific clock source in the **cpu\_mark\_t** structure. The sys\_clock field contains time with microsecond resolution. The values can later be used to measure time intervals, number of clocks, FPU frequency, etc. **See also** **cpu\_rdtsc** **Parameters** *mark* \[out\] - a pointer to a **cpu\_mark\_t** structure References **cpu\_tsc\_mark()**. Referenced by **cpu\_tsc\_mark()**. ### int cpuid\_deserialize\_all\_raw\_data (struct cpu\_raw\_data\_array\_t \* data, const char \* filename) Reads all raw CPUID data from file. **Parameters** *data* - a pointer to **cpu\_raw\_data\_array\_t** structure. The deserialized array data will be written here. \ *filename* - the path of the file, containing the serialized raw data. If empty, stdin will be used. **Note** This function may fail, if the file is created by different version of the library. Also, see the notes on cpuid\_serialize\_all\_raw\_data. As the memory is dynamically allocated, be sure to call **cpuid\_free\_raw\_data\_array()** after you're done with the data **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpuid\_deserialize\_all\_raw\_data()**. Referenced by **cpuid\_deserialize\_all\_raw\_data()**. ### int cpuid\_deserialize\_raw\_data (struct cpu\_raw\_data\_t \* data, const char \* filename) Reads raw CPUID data from file. **Parameters** *data* - a pointer to **cpu\_raw\_data\_t** structure. The deserialized data will be written here. \ *filename* - the path of the file, containing the serialized raw data. If empty, stdin will be used. **Note** This function may fail, if the file is created by different version of the library. Also, see the notes on cpuid\_serialize\_raw\_data. **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpuid\_deserialize\_raw\_data()**. Referenced by **cpuid\_deserialize\_raw\_data()**. ### void cpuid\_free\_cpu\_list (struct cpu\_list\_t \* list) Frees a CPU list. This function deletes all the memory associated with a CPU list, as obtained by **cpuid\_get\_cpu\_list()** **Parameters** *list* - the list to be free()'d. References **cpuid\_free\_cpu\_list()**. Referenced by **cpuid\_free\_cpu\_list()**. ### void cpuid\_free\_raw\_data\_array (struct cpu\_raw\_data\_array\_t \* raw\_array) Frees a raw array. This function deletes all the memory associated with a raw array, as obtained by **cpuid\_get\_all\_raw\_data()**, **cpuid\_deserialize\_all\_raw\_data()** and **cpu\_identify\_all()** **Parameters** *raw\_array* - the raw array to be free()'d. References **cpuid\_free\_raw\_data\_array()**. Referenced by **cpuid\_free\_raw\_data\_array()**. ### void cpuid\_free\_system\_id (struct system\_id\_t \* system) Frees a system ID type. This function deletes all the memory associated with a system ID, as obtained by **cpu\_identify\_all()** **Parameters** *system* - the system ID to be free()'d. References **cpuid\_free\_system\_id()**. Referenced by **cpuid\_free\_system\_id()**. ### int cpuid\_get\_all\_raw\_data (struct cpu\_raw\_data\_array\_t \* data) Obtains the raw CPUID data from all CPUs. **Parameters** *data* - a pointer to **cpu\_raw\_data\_array\_t** structure **Note** As the memory is dynamically allocated, be sure to call **cpuid\_free\_raw\_data\_array()** after you're done with the data **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpuid\_get\_all\_raw\_data()**. Referenced by **cpuid\_get\_all\_raw\_data()**. ### void cpuid\_get\_cpu\_list (cpu\_vendor\_t vendor, struct cpu\_list\_t \* list) Gets a list of all known CPU names from a specific vendor. This function compiles a list of all known CPU (code)names (i.e. the possible values of **cpu\_id\_t::cpu\_codename**) for the given vendor. There are about 100 entries for Intel and AMD, and a few for the other vendors. The list is written out in approximate chronological introduction order of the parts. **Parameters** *vendor* the vendor to be queried \ *list* \[out\] the resulting list will be written here. On failure, num\_entries is set to zero and names to NULL. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** NOTE: As the memory is dynamically allocated, be sure to call **cpuid\_free\_cpu\_list()** after you're done with the data **cpu\_list\_t** References **cpuid\_get\_cpu\_list()**. Referenced by **cpuid\_get\_cpu\_list()**. ### struct cpu\_epc\_t cpuid\_get\_epc (int index, const struct cpu\_raw\_data\_t \* raw) Fetches information about an EPC (Enclave Page Cache) area. **Parameters** *index* - zero-based index, valid range \[0..cpu\_id\_t.egx.num\_epc\_sections) \ *raw* - a pointer to fetched raw CPUID data. Needed only for testing, you can safely pass NULL here (if you pass a real structure, it will be used for fetching the leaf 12h data if index \< 2; otherwise the real CPUID instruction will be used). **Returns** the requested data. If the CPU doesn't support SGX, or if index \>= cpu\_id\_t.egx.num\_epc\_sections, both fields of the returned structure will be zeros. References **cpuid\_get\_epc()**. Referenced by **cpuid\_get\_epc()**. ### hypervisor\_vendor\_t cpuid\_get\_hypervisor (struct cpu\_raw\_data\_t \* raw, struct cpu\_id\_t \* data) Obtains the hypervisor vendor from CPUID from the current CPU. **Parameters** *raw* - Optional input - a pointer to the raw CPUID data, which is obtained either by cpuid\_get\_raw\_data or cpuid\_deserialize\_raw\_data. Can also be NULL, in which case the functions calls cpuid\_get\_raw\_data itself. \ *data* - Optional input - the decoded CPU features/info is written here. Can also be NULL, in which case the functions calls cpu\_identify itself. **Note** If no hypervisor is detected, the hypervisor can be hidden in some cases. Refer to https://github.com/anrieff/libcpuid/issues/90#issuecomment-296568713. **Returns** HYPERVISOR\_UNKNOWN if failed, HYPERVISOR\_NONE if no hypervisor detected (or hidden), otherwise the hypervisor vendor type. **See also** **hypervisor\_vendor\_t** References **cpuid\_get\_hypervisor()**. Referenced by **cpuid\_get\_hypervisor()**. ### int cpuid\_get\_raw\_data (struct cpu\_raw\_data\_t \* data) Obtains the raw CPUID data from the current CPU. **Parameters** *data* - a pointer to **cpu\_raw\_data\_t** structure **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpuid\_get\_raw\_data()**. Referenced by **cpuid\_get\_raw\_data()**. ### int cpuid\_get\_raw\_data\_core (struct cpu\_raw\_data\_t \* data, logical\_cpu\_t logical\_cpu) Obtains the raw CPUID data from the specified CPU. **Parameters** *data* - a pointer to **cpu\_raw\_data\_t** structure \ *logical\_cpu* specify the core number. The first core number is 0. The last core number is **cpuid\_get\_total\_cpus** - 1. **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpuid\_get\_raw\_data\_core()**. Referenced by **cpuid\_get\_raw\_data\_core()**. ### int cpuid\_get\_total\_cpus (void ) Returns the total number of logical CPU threads (even if CPUID is not present). Under VM, this number (and total\_logical\_cpus, since they are fetched with the same code) may be nonsensical, i.e. might not equal NumPhysicalCPUs\*NumCoresPerCPU\*HyperThreading. This is because no matter how many logical threads the host machine has, you may limit them in the VM to any number you like. **This** is the number returned by **cpuid\_get\_total\_cpus()**. **Returns** Number of logical CPU threads available. Equals the **cpu\_id\_t::total\_logical\_cpus**. References **cpuid\_get\_total\_cpus()**. Referenced by **cpuid\_get\_total\_cpus()**. ### cpu\_vendor\_t cpuid\_get\_vendor (void ) Obtains the CPU vendor from CPUID from the current CPU. **Note** The result is cached. **Returns** VENDOR\_UNKNOWN if failed, otherwise the CPU vendor type. **See also** **cpu\_vendor\_t** References **cpuid\_get\_vendor()**. Referenced by **cpuid\_get\_vendor()**. ### const char \* cpuid\_lib\_version (void ) Returns the libcpuid version. **Returns** the string representation of the libcpuid version, like "0.1.1" References **cpuid\_lib\_version()**. Referenced by **cpuid\_lib\_version()**. ### int cpuid\_present (void ) Checks if the CPUID instruction is supported. **Return values** *1* if CPUID is present \ *0* the CPU doesn't have CPUID. References **cpuid\_present()**. Referenced by **cpuid\_present()**. ### int cpuid\_serialize\_all\_raw\_data (struct cpu\_raw\_data\_array\_t \* data, const char \* filename) Writes all the raw CPUID data to a text file. **Parameters** *data* - a pointer to **cpu\_raw\_data\_array\_t** structure \ *filename* - the path of the file, where the serialized data for all CPUs should be written. If empty, stdout will be used. **Note** This is intended primarily for debugging. On some processor, which is not currently supported or not completely recognized by cpu\_identify\_all, one can still successfully get the raw data and write it to a file. libcpuid developers can later import this file and debug the detection code as if running on the actual hardware. The file is simple text format of "something=value" pairs. Version info is also written, but the format is not intended to be neither backward- nor forward compatible. **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpuid\_serialize\_all\_raw\_data()**. Referenced by **cpuid\_serialize\_all\_raw\_data()**. ### int cpuid\_serialize\_raw\_data (struct cpu\_raw\_data\_t \* data, const char \* filename) Writes the raw CPUID data to a text file. **Parameters** *data* - a pointer to **cpu\_raw\_data\_t** structure \ *filename* - the path of the file, where the serialized data should be written. If empty, stdout will be used. **Note** This is intended primarily for debugging. On some processor, which is not currently supported or not completely recognized by cpu\_identify, one can still successfully get the raw data and write it to a file. libcpuid developers can later import this file and debug the detection code as if running on the actual hardware. The file is simple text format of "something=value" pairs. Version info is also written, but the format is not intended to be neither backward- nor forward compatible. **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **cpuid\_serialize\_raw\_data()**. Referenced by **cpuid\_serialize\_raw\_data()**. ### void cpuid\_set\_verbosiness\_level (int level) Sets the verbosiness level. When the verbosiness level is above zero, some functions might print diagnostic information about what are they doing. The higher the level is, the more detail is printed. Level zero is guaranteed to omit all such output. The output is written using the same machinery as the warnings, **See also** **cpuid\_set\_warn\_function()** **Parameters** *level* the desired verbosiness level. Useful values 0..2 inclusive References **cpuid\_set\_verbosiness\_level()**. Referenced by **cpuid\_set\_verbosiness\_level()**. ### libcpuid\_warn\_fn\_t cpuid\_set\_warn\_function (libcpuid\_warn\_fn\_t warn\_fun) Sets the warning print function. In some cases, the internal libcpuid machinery would like to emit useful debug warnings. By default, these warnings are written to stderr. However, you can set a custom function that will receive those warnings. **Parameters** *warn\_fun* - the warning function you want to set. If NULL, warnings are disabled. The function takes const char\* argument. **Returns** the current warning function. You can use the return value to keep the previous warning function and restore it at your discretion. References **cpuid\_set\_warn\_function()**. Referenced by **cpuid\_set\_warn\_function()**. ### int msr\_serialize\_raw\_data (struct msr\_driver\_t \* handle, const char \* filename) Writes the raw MSR data to a text file. **Parameters** *handle* - a handle to the MSR reader driver, as created by cpu\_msr\_driver\_open \ *filename* - the path of the file, where the serialized data should be written. If empty, stdout will be used. **Note** This is intended primarily for debugging. On some processor, which is not currently supported or not completely recognized by cpu\_identify, one can still successfully get the raw data and write it to a file. libcpuid developers can later import this file and debug the detection code as if running on the actual hardware. The file is simple text format of "something=value" pairs. Version info is also written, but the format is not intended to be neither backward- nor forward compatible. **Returns** zero if successful, and some negative number on error. The error message can be obtained by calling **cpuid\_error**. **See also** **cpu\_error\_t** References **msr\_serialize\_raw\_data()**. Referenced by **msr\_serialize\_raw\_data()**. ## Author Generated automatically by Doxygen for libcpuid from the source code.