---
name: "intel_pmc"
section: "4"
platform: "freebsd"
package: "base"
version: "16.0-CURRENT-20261027-61c70dc16a79"
release: "FreeBSD 16.0-CURRENT (2026-10-27)"
platforms: ["freebsd"]
url: "https://new.carta.tech/intel_pmc"
---

# intel\_pmc(4)

Intel Performance Management Controller driver

## NAME

**intel\_pmc** – Intel Performance Management Controller driver

## SYNOPSIS

**device intel\_pmc**

## DESCRIPTION

The **intel\_pmc** driver exposes information and controls from the Performance Management Controller (PMC) of Intel platforms. Presently, it supports the Intel Sunrise Point platform (Skylake CPU generation), providing access to debug information and controls related to S0ix (Modern Standby).

The cumulative time spent in low power mode while in S0 is reported, and the administrator can force the platform to ignore IP blocks whose Latency Tolerance Reporting (LTR) prevents the platform from entering S0ix.

## HARDWARE

The **intel\_pmc** driver supports the PMC block found in the following Intel Platform Controller Hubs:

- Intel Sunrise Point-LP PMC (6th/7th Gen Core mobile, PCI ID 0x8086:0x9d21)

- Intel Sunrise Point-H PMC (6th/7th Gen Core desktop/server, PCI ID 0x8086:0xa121)

## SYSCTLS

The following [sysctl(8)](/sysctl/8.md) variables are available:

- *dev.intel\_pmc.%d.ltr\_ignore* (read-write)

  Latency Tolerance Reporting (LTR) ignore mask. Each bit corresponds to one IP block (bits 0-16). Setting a bit tells the PMC to ignore that IP's LTR requirements, allowing S0ix entry even if the IP would otherwise block it. A clear bit means the IP's requirements are considered and can prevent S0ix.

  Sunrise Point bit assignments: SOUTHPORT\_A, SOUTHPORT\_B, SATA, GIGABIT\_ETHERNET, XHCI, reserved, ME, EVA, SOUTHPORT\_C, HD\_AUDIO, LPSS, SOUTHPORT\_D, SOUTHPORT\_E, CAMERA, ESPI, SCC, ISH.

- *dev.intel\_pmc.%d.slp\_s0\_residency* (read-only)

  Cumulative time in microseconds that the SLP\_S0 signal has been asserted (100 us per counter step). Per the datasheet, SLP\_S0 asserts when the PCH is idle and the processor is in C10 state. A value that never advances indicates S0ix transitions are not occurring.

  The counter is 32-bit and wraps after approximately 5 days of cumulative S0ix residency.

## SEE ALSO

[acpi(4)](/acpi/4.md), [pci(4)](/pci/4.md), [sysctl(8)](/sysctl/8.md)

Intel 100 Series Chipset Family PCH Datasheet, Volume 2, Section 4.3.

## HISTORY

The **intel\_pmc** driver first appeared in FreeBSD 16.0.

## AUTHORS

Abdelkader Boudih ⟨*seuros@FreeBSD.org*⟩

## CAVEATS

Only Sunrise Point PCH is supported. Other PCH generations (Cannon Point, Tiger Lake, etc.) have different register layouts and are not handled by this driver.