---
name: "fnf"
section: "1"
platform: "linux"
package: "confluence"
version: "0.10.6-7+b1"
release: "Debian 8 (Jessie)"
platforms: ["linux"]
url: "https://new.carta.tech/fnf"
---

# fnf(1)

### NAME

**fnf - translate from FNF format to other formats**

### SYNOPSIS

```
    fnf [options]
```

### DESCRIPTION

**FNF (Free Netlist Format) is an elaborated, hierarchical, register transfer level (RTL)** **netlist format used to communicate design information between frontend EDA tools.**

**The FNF tool translates an FNF netlist to Verilog, VHDL, C, and NuSMV.**

### OPTIONS

**Options are processed in the order they are received.**

**-h OR -help** **Prints this information then exits.**

**-read\_fnf file** **Read in an FNF netlist.**

**-write\_fnf file** **Write out an FNF netlist.**

**-write\_nusmv file** **Write out an NuSMV description.**

**-write\_verilog file** **Write out a Verilog netlist.**

**-write\_vhdl file** **Write out a VHDL netlist.**

**-write\_c file**

- **Write out a C model.**

  **Appends '.c' and '.h' to file name.**

**-write\_jhdl class**

- **Write out a JHDL netlist.**

  **Appends .java to class name.**

### EXAMPLES

**Building an FNF netlist from Verilog using Icarus:**

```
      $ iverilog -Wall -t fnf -o my_netlist.fnf my_verilog.v
```

**Use FNF to produce a Verilog and C model:**

```
      $ fnf -read_fnf my_netlist.fnf -write_verilog my_netlist.v -write_c my_netlist
```

**Use FNF to produce an NuSMV model:**

```
      $ fnf -read_fnf my_netlist.fnf -write_nusmv my_netlist.smv
```

**Use FNF to produce another FNF netlist:**

```
      $ fnf -read_fnf my_netlist.fnf -write_fnf my_netlist2.fnf
```

### KNOWN LIMITATIONS

**General**

- •

  **No tristate support.**

- •

  **No memory support.**

- •

  **No division or modulo operators.**

**Icarus Verilog FNF Code Generator**

- •

  **Assumes ports and named signals have \[n:0\] ordering.**

- •

  **"always" blocks are constrained to the Icarus Verilog synthesizable subset.**

- •

  **All register clocks and asynchronous resets must be senitive on the rising edge.** **WARNING: No errors will be issued if a design contains "negedge".**

- •

  **All arithmetic operations must be unsigned.** **WARNING: No errors will be issued if a design contains signed operations.**

- •

  **Multipliers can not be embbeded in concatenations.**

**Verilog and VHDL Model Writer**

- •

  **Netlist is flat.**

**NuSMV Model Writer**

- **- 2-value model.**

  **No X's or Z's.**

- •

  **Inputs assumed to init to 0.**

- •

  **Registers are initialized to 0.**

### VERSION

**0.10.6**

### AUTHOR

**Tom Hawkins**

### SEE ALSO

**FNF and Confluence : http://www.confluent.org/**

- **Icarus Verilog**

  **: http://www.icarus.com/eda/verilog/**

- **NuSMV**

  **: http://nusmv.irst.itc.it/**

### COPYRIGHT

**Copyright (C) 2004-2005 Tom Hawkins**