--- name: "cpu_raw_data_t" section: "3" platform: "linux" package: "libcpuid" version: "0.8.2-1" release: "Arch Linux 2026-11-01" platforms: ["linux"] url: "https://new.carta.tech/cpu_raw_data_t" --- # cpu\_raw\_data\_t(3) Contains just the raw CPUID data. ## NAME cpu\_raw\_data\_t - Contains just the raw CPUID data. ## SYNOPSIS \#include \ ### Data Fields uint32\_t **basic\_cpuid** \[MAX\_CPUID\_LEVEL\]\[NUM\_REGS\]\ uint32\_t **ext\_cpuid** \[MAX\_EXT\_CPUID\_LEVEL\]\[NUM\_REGS\]\ uint32\_t **intel\_fn4** \[MAX\_INTELFN4\_LEVEL\]\[NUM\_REGS\]\ uint32\_t **intel\_fn11** \[MAX\_INTELFN11\_LEVEL\]\[NUM\_REGS\]\ uint32\_t **intel\_fn12h** \[MAX\_INTELFN12H\_LEVEL\]\[NUM\_REGS\]\ uint32\_t **intel\_fn14h** \[MAX\_INTELFN14H\_LEVEL\]\[NUM\_REGS\]\ uint32\_t **amd\_fn8000001dh** \[MAX\_AMDFN8000001DH\_LEVEL\]\[NUM\_REGS\]\ uint32\_t **amd\_fn80000026h** \[MAX\_AMDFN80000026H\_LEVEL\]\[NUM\_REGS\]\ uint64\_t **arm\_midr**\ uint64\_t **arm\_mpidr**\ uint64\_t **arm\_revidr**\ uint32\_t **arm\_id\_afr** \[MAX\_ARM\_ID\_AFR\_REGS\]\ uint32\_t **arm\_id\_dfr** \[MAX\_ARM\_ID\_DFR\_REGS\]\ uint32\_t **arm\_id\_isar** \[MAX\_ARM\_ID\_ISAR\_REGS\]\ uint32\_t **arm\_id\_mmfr** \[MAX\_ARM\_ID\_MMFR\_REGS\]\ uint32\_t **arm\_id\_pfr** \[MAX\_ARM\_ID\_PFR\_REGS\]\ uint64\_t **arm\_id\_aa64afr** \[MAX\_ARM\_ID\_AA64AFR\_REGS\]\ uint64\_t **arm\_id\_aa64dfr** \[MAX\_ARM\_ID\_AA64DFR\_REGS\]\ uint64\_t **arm\_id\_aa64fpfr** \[MAX\_ARM\_ID\_AA64FPFR\_REGS\]\ uint64\_t **arm\_id\_aa64isar** \[MAX\_ARM\_ID\_AA64ISAR\_REGS\]\ uint64\_t **arm\_id\_aa64mmfr** \[MAX\_ARM\_ID\_AA64MMFR\_REGS\]\ uint64\_t **arm\_id\_aa64pfr** \[MAX\_ARM\_ID\_AA64PFR\_REGS\]\ uint64\_t **arm\_id\_aa64smfr** \[MAX\_ARM\_ID\_AA64SMFR\_REGS\]\ uint64\_t **arm\_id\_aa64zfr** \[MAX\_ARM\_ID\_AA64ZFR\_REGS\]\ ## Detailed Description Contains just the raw CPUID data. This contains only the most basic CPU data, required to do identification and feature recognition. Every processor should be identifiable using this data only. ## Field Documentation ### uint32\_t cpu\_raw\_data\_t::amd\_fn8000001dh\[MAX\_AMDFN8000001DH\_LEVEL\]\[NUM\_REGS\] when the CPU is AMD and supports leaf 8000001Dh (topology information for the DC) this stores the result of CPUID with eax = 8000001Dh and ecx = 0, 1, 2... ### uint32\_t cpu\_raw\_data\_t::amd\_fn80000026h\[MAX\_AMDFN80000026H\_LEVEL\]\[NUM\_REGS\] when the CPU is AMD and supports leaf 80000026h (Extended CPU Topology leaf) this stores the result of CPUID with eax = 80000026h and ecx = 0, 1, 2... ### uint64\_t cpu\_raw\_data\_t::arm\_id\_aa64afr\[MAX\_ARM\_ID\_AA64AFR\_REGS\] when then CPU is ARM-based and supports ID\_AA64AFR\* (AArch64 Auxiliary Feature Register) ### uint64\_t cpu\_raw\_data\_t::arm\_id\_aa64dfr\[MAX\_ARM\_ID\_AA64DFR\_REGS\] when then CPU is ARM-based and supports ID\_AA64DFR\* (AArch64 Debug Feature Register) ### uint64\_t cpu\_raw\_data\_t::arm\_id\_aa64fpfr\[MAX\_ARM\_ID\_AA64FPFR\_REGS\] when then CPU is ARM-based and supports ID\_AA64FPFR\* (Floating-point Feature Register) ### uint64\_t cpu\_raw\_data\_t::arm\_id\_aa64isar\[MAX\_ARM\_ID\_AA64ISAR\_REGS\] when then CPU is ARM-based and supports D\_AA64ISAR\* (AArch64 Instruction Set Attribute Register) ### uint64\_t cpu\_raw\_data\_t::arm\_id\_aa64mmfr\[MAX\_ARM\_ID\_AA64MMFR\_REGS\] when then CPU is ARM-based and supports ID\_AA64MMFR\* (AArch64 Memory Model Feature Register) ### uint64\_t cpu\_raw\_data\_t::arm\_id\_aa64pfr\[MAX\_ARM\_ID\_AA64PFR\_REGS\] when then CPU is ARM-based and supports ID\_AA64PFR\* (AArch64 Processor Feature Register) ### uint64\_t cpu\_raw\_data\_t::arm\_id\_aa64smfr\[MAX\_ARM\_ID\_AA64SMFR\_REGS\] when then CPU is ARM-based and supports ID\_AA64SMFR\* (AArch64 SME Feature ID Register ) ### uint64\_t cpu\_raw\_data\_t::arm\_id\_aa64zfr\[MAX\_ARM\_ID\_AA64ZFR\_REGS\] when then CPU is ARM-based and supports ID\_AA64ZFR\* (SVE Feature ID register) ### uint32\_t cpu\_raw\_data\_t::arm\_id\_afr\[MAX\_ARM\_ID\_AFR\_REGS\] when then CPU is ARM-based and supports ID\_AFR\* (AArch32 Auxiliary Feature Register) ### uint32\_t cpu\_raw\_data\_t::arm\_id\_dfr\[MAX\_ARM\_ID\_DFR\_REGS\] when then CPU is ARM-based and supports ID\_DFR\* (AArch32 Debug Feature Register) ### uint32\_t cpu\_raw\_data\_t::arm\_id\_isar\[MAX\_ARM\_ID\_ISAR\_REGS\] when then CPU is ARM-based and supports D\_ISAR\* (AArch32 Instruction Set Attribute Register) ### uint32\_t cpu\_raw\_data\_t::arm\_id\_mmfr\[MAX\_ARM\_ID\_MMFR\_REGS\] when then CPU is ARM-based and supports ID\_MMFR\* (AArch32 Memory Model Feature Register) ### uint32\_t cpu\_raw\_data\_t::arm\_id\_pfr\[MAX\_ARM\_ID\_PFR\_REGS\] when then CPU is ARM-based and supports ID\_PFR\* (AArch32 Processor Feature Register) ### uint64\_t cpu\_raw\_data\_t::arm\_midr when then CPU is ARM-based and supports MIDR (Main ID Register) ### uint64\_t cpu\_raw\_data\_t::arm\_mpidr when then CPU is ARM-based and supports MPIDR (Multiprocessor Affinity Register) ### uint64\_t cpu\_raw\_data\_t::arm\_revidr when then CPU is ARM-based and supports REVIDR (Revision ID Register) ### uint32\_t cpu\_raw\_data\_t::basic\_cpuid\[MAX\_CPUID\_LEVEL\]\[NUM\_REGS\] contains results of CPUID for eax = 0, 1, ... ### uint32\_t cpu\_raw\_data\_t::ext\_cpuid\[MAX\_EXT\_CPUID\_LEVEL\]\[NUM\_REGS\] contains results of CPUID for eax = 0x80000000, 0x80000001, ... ### uint32\_t cpu\_raw\_data\_t::intel\_fn11\[MAX\_INTELFN11\_LEVEL\]\[NUM\_REGS\] when the CPU is intel and it supports leaf 0Bh (Extended Topology enumeration leaf), this stores the result of CPUID with eax = 11 and ecx = 0, 1, 2... ### uint32\_t cpu\_raw\_data\_t::intel\_fn12h\[MAX\_INTELFN12H\_LEVEL\]\[NUM\_REGS\] when the CPU is intel and supports leaf 12h (SGX enumeration leaf), this stores the result of CPUID with eax = 0x12 and ecx = 0, 1, 2... ### uint32\_t cpu\_raw\_data\_t::intel\_fn14h\[MAX\_INTELFN14H\_LEVEL\]\[NUM\_REGS\] when the CPU is intel and supports leaf 14h (Intel Processor Trace capabilities leaf). this stores the result of CPUID with eax = 0x12 and ecx = 0, 1, 2... ### uint32\_t cpu\_raw\_data\_t::intel\_fn4\[MAX\_INTELFN4\_LEVEL\]\[NUM\_REGS\] when the CPU is intel and it supports deterministic cache information: this contains the results of CPUID for eax = 4 and ecx = 0, 1, ... ## Author Generated automatically by Doxygen for libcpuid from the source code.