---
name: "cpu_id_t"
section: "3"
platform: "linux"
package: "libcpuid"
version: "0.8.2-1"
release: "Arch Linux 2026-11-01"
platforms: ["linux"]
url: "https://new.carta.tech/cpu_id_t"
---

# cpu\_id\_t(3)

This contains the recognized CPU features/info.

## NAME

cpu\_id\_t - This contains the recognized CPU features/info.

## SYNOPSIS

\#include \<libcpuid.h\>

### Data Structures

union **\[union\].\_\_unnamed0\_\_**\

### Data Fields

**cpu\_architecture\_t** **architecture**\
 **cpu\_feature\_level\_t** **feature\_level**\
 char **vendor\_str** \[VENDOR\_STR\_MAX\]\
 char **brand\_str** \[BRAND\_STR\_MAX\]\
 **cpu\_vendor\_t** **vendor**\
 uint8\_t **flags** \[CPU\_FLAGS\_MAX\]\
 int32\_t **family**\
 int32\_t **model**\
 int32\_t **stepping**\
 int32\_t **ext\_family**\
 int32\_t **ext\_model**\
 **union**  \
 int32\_t **num\_cores**\
 int32\_t **num\_logical\_cpus**\
 int32\_t **total\_logical\_cpus**\
 int32\_t **l1\_data\_cache**\
 int32\_t **l1\_instruction\_cache**\
 int32\_t **l2\_cache**\
 int32\_t **l3\_cache**\
 int32\_t **l4\_cache**\
 int32\_t **l1\_assoc**\
 int32\_t **l1\_data\_assoc**\
 int32\_t **l1\_instruction\_assoc**\
 int32\_t **l2\_assoc**\
 int32\_t **l3\_assoc**\
 int32\_t **l4\_assoc**\
 int32\_t **l1\_cacheline**\
 int32\_t **l1\_data\_cacheline**\
 int32\_t **l1\_instruction\_cacheline**\
 int32\_t **l2\_cacheline**\
 int32\_t **l3\_cacheline**\
 int32\_t **l4\_cacheline**\
 int32\_t **l1\_data\_instances**\
 int32\_t **l1\_instruction\_instances**\
 int32\_t **l2\_instances**\
 int32\_t **l3\_instances**\
 int32\_t **l4\_instances**\
 char **cpu\_codename** \[CODENAME\_STR\_MAX\]\
 int32\_t **sse\_size**\
 uint8\_t **detection\_hints** \[CPU\_HINTS\_MAX\]\
 struct **cpu\_sgx\_t** **sgx**\
 **cpu\_affinity\_mask\_t** **affinity\_mask**\
 **cpu\_purpose\_t** **purpose**\
 char **technology\_node** \[TECHNOLOGY\_STR\_MAX\]\

## Detailed Description

This contains the recognized CPU features/info.

## Field Documentation

### cpu\_affinity\_mask\_t cpu\_id\_t::affinity\_mask

bitmask of the affinity ids this processor type is occupying

### cpu\_architecture\_t cpu\_id\_t::architecture

contains the CPU architecture ID (e.g. ARCHITECTURE\_X86)

### char cpu\_id\_t::brand\_str\[BRAND\_STR\_MAX\]

contains the brand string, e.g. "Intel(R) Xeon(TM) CPU 2.40GHz"

### char cpu\_id\_t::cpu\_codename\[CODENAME\_STR\_MAX\]

The brief and human-friendly CPU codename, which was recognized.\
\
  Examples:

```
+--------+--------+-------+-------+-------+---------------------------------------+-----------------------+
| Vendor | Family | Model | Step. | Cache |       Brand String                    | cpu_id_t.cpu_codename |
+--------+--------+-------+-------+-------+---------------------------------------+-----------------------+
| AMD    |      6 |     8 |     0 |   256 | (not available - will be ignored)     | "K6-2"                |
| Intel  |     15 |     2 |     5 |   512 | "Intel(R) Xeon(TM) CPU 2.40GHz"       | "Xeon (Prestonia)"    |
| Intel  |      6 |    15 |    11 |  4096 | "Intel(R) Core(TM)2 Duo CPU E6550..." | "Conroe (Core 2 Duo)" |
| AMD    |     15 |    35 |     2 |  1024 | "Dual Core AMD Opteron(tm) Proces..." | "Opteron (Dual Core)" |
+--------+--------+-------+-------+-------+---------------------------------------+-----------------------+
```

### uint8\_t cpu\_id\_t::detection\_hints\[CPU\_HINTS\_MAX\]

contain miscellaneous detection information. Used to test about specifics of certain detected features. See **CPU\_HINT\_\*** macros below.

**See also**

Hints

### int32\_t cpu\_id\_t::ext\_family

CPU display ("true") family (computed as BaseFamily\[3:0\]+ExtendedFamily\[7:0\])

**Deprecated**

replaced by **x86\_id\_t::ext\_family** (prefix member with x86., e.g. id.x86.ext\_family)

### int32\_t cpu\_id\_t::ext\_model

CPU display ("true") model (computed as (ExtendedModel\[3:0\]\<\<4) + BaseModel\[3:0\]) For detailed discussion about what BaseModel / ExtendedModel / Model are, see Github issue #150.

**Deprecated**

replaced by **x86\_id\_t::ext\_model** (prefix member with x86., e.g. id.x86.ext\_model)

### int32\_t cpu\_id\_t::family

CPU family (BaseFamily\[3:0\])

**Deprecated**

replaced by **x86\_id\_t::family** (prefix member with x86., e.g. id.x86.family)

### cpu\_feature\_level\_t cpu\_id\_t::feature\_level

contains the CPU feature level, also know as microarchitecture levels (x86) and architecture version (ARM)

### uint8\_t cpu\_id\_t::flags\[CPU\_FLAGS\_MAX\]

contain CPU flags. Used to test for features. See the **CPU\_FEATURE\_\*** macros below.

**See also**

Features

### int32\_t cpu\_id\_t::l1\_assoc

Cache associativity for the L1 data cache. -1 if undetermined

**Deprecated**

replaced by **cpu\_id\_t::l1\_data\_assoc**

### int32\_t cpu\_id\_t::l1\_cacheline

Cache-line size for L1 data cache. -1 if undetermined

**Deprecated**

replaced by **cpu\_id\_t::l1\_data\_cacheline**

### int32\_t cpu\_id\_t::l1\_data\_assoc

Cache associativity for the L1 data cache. -1 if undetermined

### int32\_t cpu\_id\_t::l1\_data\_cache

L1 data cache size in KB. Could be zero, if the CPU lacks cache. If the size cannot be determined, it will be -1.

### int32\_t cpu\_id\_t::l1\_data\_cacheline

Cache-line size for L1 data cache. -1 if undetermined

### int32\_t cpu\_id\_t::l1\_data\_instances

Number of L1 data cache instances. -1 if undetermined

### int32\_t cpu\_id\_t::l1\_instruction\_assoc

Cache associativity for the L1 instruction cache. -1 if undetermined

### int32\_t cpu\_id\_t::l1\_instruction\_cache

L1 instruction cache size in KB. Could be zero, if the CPU lacks cache. If the size cannot be determined, it will be -1.

**Note**

On some Intel CPUs, whose instruction cache is in fact a trace cache, the size will be expressed in K uOps.

### int32\_t cpu\_id\_t::l1\_instruction\_cacheline

Cache-line size for L1 instruction cache. -1 if undetermined

### int32\_t cpu\_id\_t::l1\_instruction\_instances

Number of L1 instruction cache instances. -1 if undetermined

### int32\_t cpu\_id\_t::l2\_assoc

Cache associativity for the L2 cache. -1 if undetermined

### int32\_t cpu\_id\_t::l2\_cache

L2 cache size in KB. Could be zero, if the CPU lacks L2 cache. If the size of the cache could not be determined, it will be -1

### int32\_t cpu\_id\_t::l2\_cacheline

Cache-line size for L2 cache. -1 if undetermined

### int32\_t cpu\_id\_t::l2\_instances

Number of L2 cache instances. -1 if undetermined

### int32\_t cpu\_id\_t::l3\_assoc

Cache associativity for the L3 cache. -1 if undetermined

### int32\_t cpu\_id\_t::l3\_cache

L3 cache size in KB. Zero on most systems

### int32\_t cpu\_id\_t::l3\_cacheline

Cache-line size for L3 cache. -1 if undetermined

### int32\_t cpu\_id\_t::l3\_instances

Number of L3 cache instances. -1 if undetermined

### int32\_t cpu\_id\_t::l4\_assoc

Cache associativity for the L4 cache. -1 if undetermined

### int32\_t cpu\_id\_t::l4\_cache

L4 cache size in KB. Zero on most systems

### int32\_t cpu\_id\_t::l4\_cacheline

Cache-line size for L4 cache. -1 if undetermined

### int32\_t cpu\_id\_t::l4\_instances

Number of L4 cache instances. -1 if undetermined

### int32\_t cpu\_id\_t::model

CPU model (BaseModel\[3:0\])

**Deprecated**

replaced by **x86\_id\_t::model** (prefix member with x86., e.g. id.x86.model)

### int32\_t cpu\_id\_t::num\_cores

Number of CPU cores on the current processor

### int32\_t cpu\_id\_t::num\_logical\_cpus

Number of logical processors on the current processor. Could be more than the number of physical cores, e.g. when the processor has HyperThreading.

### cpu\_purpose\_t cpu\_id\_t::purpose

processor type purpose, relevant in case of hybrid CPU (e.g. PURPOSE\_PERFORMANCE)

### struct cpu\_sgx\_t cpu\_id\_t::sgx

contains information about SGX features if the processor, if present

**Deprecated**

replaced by **x86\_id\_t::sgx** (prefix member with x86., e.g. id.x86.sgx)

### int32\_t cpu\_id\_t::sse\_size

SSE execution unit size (64 or 128; -1 if N/A)

**Deprecated**

replaced by **x86\_id\_t::sse\_size** (prefix member with x86., e.g. id.x86.sse\_size)

### int32\_t cpu\_id\_t::stepping

CPU stepping

**Deprecated**

replaced by **x86\_id\_t::stepping** (prefix member with x86., e.g. id.x86.stepping)

### char cpu\_id\_t::technology\_node\[TECHNOLOGY\_STR\_MAX\]

contains the technology node string, e.g. "32 nm"

### int32\_t cpu\_id\_t::total\_logical\_cpus

The total number of logical processors. The same value is available through **cpuid\_get\_total\_cpus**.

This is num\_logical\_cpus \* {total physical processors in the system} (but only on a real system, under a VM this number may be lower).

If you're writing a multithreaded program and you want to run it on all CPUs, this is the number of threads you need.

**Note**

in a VM, this will exactly match the number of CPUs set in the VM's configuration.

### cpu\_vendor\_t cpu\_id\_t::vendor

contains the recognized CPU vendor

### char cpu\_id\_t::vendor\_str\[VENDOR\_STR\_MAX\]

contains the CPU vendor string, e.g. "GenuineIntel"

## Author

Generated automatically by Doxygen for libcpuid from the source code.