---
name: "Verilog::Netlist::Module"
section: "3pm"
platform: "linux"
package: "libverilog-perl"
version: "3.482-2"
release: "Debian 13 (Trixie)"
platforms: ["linux"]
url: "https://new.carta.tech/Verilog::Netlist::Module"
---

# Verilog::Netlist::Module(3pm)

Module within a Verilog Netlist

## NAME

Verilog::Netlist::Module - Module within a Verilog Netlist

## SYNOPSIS

```
  use Verilog::Netlist;
  ...
  my $module = $netlist->find_module('modname');
  my $cell = $self->find_cell('name')
  my $port =  $self->find_port('name')
  my $net =  $self->find_net('name')
```

## DESCRIPTION

A Verilog::Netlist::Module object is created by Verilog::Netlist for every module, macromodule, primitive or program in the design.

## ACCESSORS

See also Verilog::Netlist::Subclass for additional accessors and methods.

- $self-\>cells

  Returns list of references to Verilog::Netlist::Cell in the module.

- $self-\>cells\_sorted

  Returns list of name sorted references to Verilog::Netlist::Cell in the module.

- $self-\>comment

  Returns any comments following the definition.  keep\_comments=\>1 must be passed to Verilog::Netlist::new for comments to be retained.

- $self-\>find\_port\_by\_index

  Returns the port name associated with the given index.  Indexes start at 1 (pin numbers are traditionally counted from pin 1..pin N, not starting at zero.  This was probably an unfortunate choice, sorry.)

- $self-\>is\_top

  Returns true if the module has no cells referencing it (is at the top of the hierarchy.)

- $self-\>keyword

  Returns the keyword used to declare the module ("module", "macromodule", "primitive" or "program".)  It might at first not seem obvious that programs are considered modules, but in most cases they contain the same type of objects so can be handled identically.

- $self-\>name

  The name of the module.

- $self-\>netlist

  Reference to the Verilog::Netlist the module is under.

- $self-\>nets

  Returns list of references to Verilog::Netlist::Net in the module.

- $self-\>nets\_sorted

  Returns list of name sorted references to Verilog::Netlist::Net in the module.

- $self-\>nets\_and\_ports\_sorted

  Returns list of name sorted references to Verilog::Netlist::Net and Verilog::Netlist::Port in the module.

- $self-\>ports

  Returns list of references to Verilog::Netlist::Port in the module.

- $self-\>ports\_ordered

  Returns list of references to Verilog::Netlist::Port in the module sorted by pin number.

- $self-\>ports\_sorted

  Returns list of references to Verilog::Netlist::Port in the module sorted by name.

- $self-\>statements

  Returns list of references to Verilog::Netlist::ContAssign in the module. Other statement types (Always, etc) may also be added to this list in the future.

- $self-\>statements\_sorted

  Returns list of name sorted references to Verilog::Netlist::ContAssign in the module.  Other statement types (Always, etc) may also be added to this list in the future.

## MEMBER FUNCTIONS

See also Verilog::Netlist::Subclass for additional accessors and methods.

- $self-\>find\_cell(*name*)

  Returns Verilog::Netlist::Cell matching given name.

- $self-\>find\_port(*name*)

  Returns Verilog::Netlist::Port matching given name.

- $self-\>find\_net(*name*)

  Returns Verilog::Netlist::Net matching given name.

- $self-\>is\_libcell

  Returns if module declared inside a \`celldefine.

- $self-\>level

  Returns the reverse depth of this module with respect to other modules. Leaf modules (modules with no cells) will be level 1.  Modules which instantiate cells of level 1 will be level 2 modules and so forth.  See also Netlist's modules\_sorted\_level.

- $self-\>lint

  Checks the module for errors.

- $self-\>link

  Creates interconnections between this module and other modules.

- $self-\>modulename\_from\_filename

  Uses a rough algorithm (drop the extension) to convert a filename to the module that is expected to be inside it.

- $self-\>new\_cell

  Creates a new Verilog::Netlist::Cell.

- $self-\>new\_port

  Creates a new Verilog::Netlist::Port.

- $self-\>new\_net

  Creates a new Verilog::Netlist::Net.

- $self-\>dump

  Prints debugging information for this module.

- $self-\>verilog\_text

  Returns verilog code which represents this module.  Returned as an array that must be joined together to form the final text string.  The netlist must be already -\>link'ed for this to work correctly.

## DISTRIBUTION

Verilog-Perl is part of the \<https://www.veripool.org/\> free Verilog EDA software tool suite.  The latest version is available from CPAN and from \<https://www.veripool.org/verilog-perl\>.

Copyright 2000-2024 by Wilson Snyder.  This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

## AUTHORS

Wilson Snyder \<wsnyder@wsnyder.org\>

## SEE ALSO

Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist