---
name: "DPGEN_RF1D"
section: "3"
platform: "linux"
package: "alliance"
version: "5.1.1-3"
release: "Debian 10 (Buster)"
platforms: ["linux"]
url: "https://new.carta.tech/DPGEN_RF1D"
---

# DPGEN\_RF1D(3)

Register File with Decoder Macro-Generator

## NAME

DPGEN\_RF1D, DPGEN\_RF1DR0 - Register File with Decoder Macro-Generator

## SYNOPSIS

**#include  \<genlib.h\>**

**void GENLIB\_MACRO (DPGEN\_RF1D, char \****modelname***, long** *flags***, long** *N***);**

**void GENLIB\_MACRO (DPGEN\_RF1DR0, char \****modelname***, long** *flags***, long** *N***);**

## DESCRIPTION

Generate a register file of *regNumber* words of *N* bits with decoder named *modelname*. The DPGEN\_RF1DR0 variant differs from the DPGEN\_RF1D in that the register of address zero is stuck to zero. You can write into it, it will not change the value. When read, it will always return zero.

How it works :

- •

  datain0 and datain1 : the two write busses. Only one is used to actually write the register word, it is selected by the sel signal.

- •

  sel : when set to '0' the datain0 is used to write the register word, otherwise it will be datain1.

- •

  adr, adw : the width (*Y*) of those signals is computed from *regNumber* : Y = log2(regNumber).

- •

  wen and ren : write enable and read enable, allows reading and writing when sets to '1'.

### TERMINAL NAMES

- 1\.

  ck : clock signal (input, 1 bit).

- 2\.

  sel : select the write bus (input, 1 bit).

- 3\.

  wen : write enable (input, 1 bit).

- 4\.

  ren : read enable (input, 1 bit).

- 5\.

  adr : the read address (input, *Y* bits).

- 6\.

  adw : the write address (input, *Y* bits).

- 7\.

  datain0 :  first write bus (input, *N* bits).

- 8\.

  datain1 :  second write bus (input, *N* bits).

- 9\.

  dataout : read bus (output, *N* bits).

- 10\.

  vdd : power.

- 11\.

  vss : ground.

## EXAMPLE

```
GENLIB_MACRO(DPGEN_RF1D, "model_rf1dx8_32"
                       , F_BEHAV|F_PLACE
                       , 32  /* Words size.      */
                       , 8   /* Number of words. */
                       );
GENLIB_LOINS( "model_rf1dx8_32"
            , "instance1_rf1d_32"
            , "ck"
            , "sel"
            , "wen"
            , "ren"
            , "adr[2:0]"
            , "adw[2:0]"
            , "datain0[31:0]"
            , "datain1[31:0]"
            , "dataout[31:0]"
            , "vdd", "vss", NULL
            );
```

## SEE ALSO

[**GENLIB\_MACRO**(3)](/GENLIB_MACRO/3.md), [**genlib**(1)](/genlib/1.md)